49ea7fc094
PXA95x isn't widely used. And it adds the effort on supporting multiple platform. So remove it. The assumption is that nobody will miss this support. If you are reading this text because you actually require pxa95x support on a new kernel, we can work out a way to revert this patch or add support to the mmp platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
311 lines
6.8 KiB
C
311 lines
6.8 KiB
C
/*
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* arch/arm/mach-pxa/include/mach/hardware.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <mach/addr-map.h>
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/*
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* Workarounds for at least 2 errata so far require this.
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* The mapping is set in mach-pxa/generic.c.
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*/
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#define UNCACHED_PHYS_0 0xff000000
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#define UNCACHED_ADDR UNCACHED_PHYS_0
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/*
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* Intel PXA2xx internal register mapping:
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*
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* 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
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* 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
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* 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
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* 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
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* 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
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* 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
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* 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
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*
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* Note that not all PXA2xx chips implement all those addresses, and the
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* kernel only maps the minimum needed range of this mapping.
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*/
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#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
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#define io_p2v(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
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#ifndef __ASSEMBLY__
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# define __REG(x) (*((volatile u32 __iomem *)io_p2v(x)))
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/* With indexed regs we don't want to feed the index through io_p2v()
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especially if it is a variable, otherwise horrible code will result. */
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# define __REG2(x,y) \
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(*(volatile u32 __iomem*)((u32)&__REG(x) + (y)))
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# define __PREG(x) (io_v2p((u32)&(x)))
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#else
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# define __REG(x) io_p2v(x)
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# define __PREG(x) io_v2p(x)
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#endif
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#ifndef __ASSEMBLY__
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#include <asm/cputype.h>
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/*
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* CPU Stepping CPU_ID JTAG_ID
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*
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* PXA210 B0 0x69052922 0x2926C013
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* PXA210 B1 0x69052923 0x3926C013
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* PXA210 B2 0x69052924 0x4926C013
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* PXA210 C0 0x69052D25 0x5926C013
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*
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* PXA250 A0 0x69052100 0x09264013
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* PXA250 A1 0x69052101 0x19264013
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* PXA250 B0 0x69052902 0x29264013
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* PXA250 B1 0x69052903 0x39264013
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* PXA250 B2 0x69052904 0x49264013
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* PXA250 C0 0x69052D05 0x59264013
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*
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* PXA255 A0 0x69052D06 0x69264013
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*
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* PXA26x A0 0x69052903 0x39264013
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* PXA26x B0 0x69052D05 0x59264013
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*
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* PXA27x A0 0x69054110 0x09265013
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* PXA27x A1 0x69054111 0x19265013
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* PXA27x B0 0x69054112 0x29265013
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* PXA27x B1 0x69054113 0x39265013
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* PXA27x C0 0x69054114 0x49265013
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* PXA27x C5 0x69054117 0x79265013
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*
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* PXA30x A0 0x69056880 0x0E648013
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* PXA30x A1 0x69056881 0x1E648013
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* PXA31x A0 0x69056890 0x0E649013
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* PXA31x A1 0x69056891 0x1E649013
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* PXA31x A2 0x69056892 0x2E649013
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* PXA32x B1 0x69056825 0x5E642013
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* PXA32x B2 0x69056826 0x6E642013
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*
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* PXA930 B0 0x69056835 0x5E643013
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* PXA930 B1 0x69056837 0x7E643013
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* PXA930 B2 0x69056838 0x8E643013
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*
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* PXA935 A0 0x56056931 0x1E653013
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* PXA935 B0 0x56056936 0x6E653013
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* PXA935 B1 0x56056938 0x8E653013
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*/
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#ifdef CONFIG_PXA25x
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#define __cpu_is_pxa210(id) \
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({ \
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unsigned int _id = (id) & 0xf3f0; \
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_id == 0x2120; \
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})
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#define __cpu_is_pxa250(id) \
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({ \
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unsigned int _id = (id) & 0xf3ff; \
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_id <= 0x2105; \
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})
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#define __cpu_is_pxa255(id) \
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({ \
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unsigned int _id = (id) & 0xffff; \
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_id == 0x2d06; \
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})
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#define __cpu_is_pxa25x(id) \
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({ \
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unsigned int _id = (id) & 0xf300; \
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_id == 0x2100; \
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})
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#else
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#define __cpu_is_pxa210(id) (0)
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#define __cpu_is_pxa250(id) (0)
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#define __cpu_is_pxa255(id) (0)
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#define __cpu_is_pxa25x(id) (0)
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#endif
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#ifdef CONFIG_PXA27x
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#define __cpu_is_pxa27x(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x411; \
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})
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#else
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#define __cpu_is_pxa27x(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA300
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#define __cpu_is_pxa300(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x688; \
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})
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#else
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#define __cpu_is_pxa300(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA310
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#define __cpu_is_pxa310(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x689; \
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})
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#else
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#define __cpu_is_pxa310(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA320
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#define __cpu_is_pxa320(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x603 || _id == 0x682; \
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})
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#else
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#define __cpu_is_pxa320(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA930
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#define __cpu_is_pxa930(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x683; \
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})
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#else
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#define __cpu_is_pxa930(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA935
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#define __cpu_is_pxa935(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x693; \
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})
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#else
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#define __cpu_is_pxa935(id) (0)
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#endif
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#define cpu_is_pxa210() \
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({ \
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__cpu_is_pxa210(read_cpuid_id()); \
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})
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#define cpu_is_pxa250() \
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({ \
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__cpu_is_pxa250(read_cpuid_id()); \
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})
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#define cpu_is_pxa255() \
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({ \
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__cpu_is_pxa255(read_cpuid_id()); \
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})
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#define cpu_is_pxa25x() \
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({ \
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__cpu_is_pxa25x(read_cpuid_id()); \
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})
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#define cpu_is_pxa27x() \
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({ \
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__cpu_is_pxa27x(read_cpuid_id()); \
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})
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#define cpu_is_pxa300() \
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({ \
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__cpu_is_pxa300(read_cpuid_id()); \
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})
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#define cpu_is_pxa310() \
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({ \
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__cpu_is_pxa310(read_cpuid_id()); \
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})
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#define cpu_is_pxa320() \
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({ \
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__cpu_is_pxa320(read_cpuid_id()); \
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})
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#define cpu_is_pxa930() \
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({ \
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__cpu_is_pxa930(read_cpuid_id()); \
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})
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#define cpu_is_pxa935() \
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({ \
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__cpu_is_pxa935(read_cpuid_id()); \
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})
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/*
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* CPUID Core Generation Bit
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* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
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*/
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#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
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#define __cpu_is_pxa2xx(id) \
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({ \
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unsigned int _id = (id) >> 13 & 0x7; \
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_id <= 0x2; \
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})
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#else
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#define __cpu_is_pxa2xx(id) (0)
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#endif
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#ifdef CONFIG_PXA3xx
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#define __cpu_is_pxa3xx(id) \
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({ \
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__cpu_is_pxa300(id) \
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|| __cpu_is_pxa310(id) \
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|| __cpu_is_pxa320(id) \
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|| __cpu_is_pxa93x(id); \
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})
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#else
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#define __cpu_is_pxa3xx(id) (0)
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#endif
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#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
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#define __cpu_is_pxa93x(id) \
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({ \
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__cpu_is_pxa930(id) \
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|| __cpu_is_pxa935(id); \
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})
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#else
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#define __cpu_is_pxa93x(id) (0)
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#endif
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#define cpu_is_pxa2xx() \
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({ \
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__cpu_is_pxa2xx(read_cpuid_id()); \
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})
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#define cpu_is_pxa3xx() \
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({ \
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__cpu_is_pxa3xx(read_cpuid_id()); \
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})
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#define cpu_is_pxa93x() \
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({ \
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__cpu_is_pxa93x(read_cpuid_id()); \
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})
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/*
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* return current memory and LCD clock frequency in units of 10kHz
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*/
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extern unsigned int get_memclk_frequency_10khz(void);
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/* return the clock tick rate of the OS timer */
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extern unsigned long get_clock_tick_rate(void);
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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