314 lines
8.6 KiB
C
314 lines
8.6 KiB
C
/*
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* This file is based on code from OCTEON SDK by Cavium Networks.
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*
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* Copyright (c) 2003-2007 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/netdevice.h>
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#include <linux/interrupt.h>
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#include <linux/phy.h>
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#include <linux/ratelimit.h>
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#include <net/dst.h>
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#include <asm/octeon/octeon.h>
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#include "ethernet-defines.h"
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#include "octeon-ethernet.h"
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#include "ethernet-util.h"
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#include "ethernet-mdio.h"
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-ipd-defs.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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static DEFINE_SPINLOCK(global_register_lock);
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static int number_rgmii_ports;
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static void cvm_oct_set_hw_preamble(struct octeon_ethernet *priv, bool enable)
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{
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union cvmx_gmxx_rxx_frm_ctl gmxx_rxx_frm_ctl;
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union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs;
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union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
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int interface = INTERFACE(priv->port);
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int index = INDEX(priv->port);
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/* Set preamble checking. */
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gmxx_rxx_frm_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL(index,
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interface));
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gmxx_rxx_frm_ctl.s.pre_chk = enable;
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cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(index, interface),
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gmxx_rxx_frm_ctl.u64);
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/* Set FCS stripping. */
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ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS);
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if (enable)
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ipd_sub_port_fcs.s.port_bit |= 1ull << priv->port;
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else
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ipd_sub_port_fcs.s.port_bit &=
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0xffffffffull ^ (1ull << priv->port);
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cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64);
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/* Clear any error bits. */
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gmxx_rxx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index,
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interface));
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cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
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gmxx_rxx_int_reg.u64);
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}
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static void cvm_oct_rgmii_poll(struct net_device *dev)
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{
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struct octeon_ethernet *priv = netdev_priv(dev);
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unsigned long flags = 0;
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cvmx_helper_link_info_t link_info;
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int use_global_register_lock = (priv->phydev == NULL);
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BUG_ON(in_interrupt());
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if (use_global_register_lock) {
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/*
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* Take the global register lock since we are going to
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* touch registers that affect more than one port.
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*/
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spin_lock_irqsave(&global_register_lock, flags);
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} else {
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mutex_lock(&priv->phydev->bus->mdio_lock);
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}
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link_info = cvmx_helper_link_get(priv->port);
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if (link_info.u64 == priv->link_info) {
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if (link_info.s.speed == 10) {
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/*
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* Read the GMXX_RXX_INT_REG[PCTERR] bit and
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* see if we are getting preamble errors.
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*/
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int interface = INTERFACE(priv->port);
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int index = INDEX(priv->port);
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union cvmx_gmxx_rxx_int_reg gmxx_rxx_int_reg;
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gmxx_rxx_int_reg.u64 =
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cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
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(index, interface));
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if (gmxx_rxx_int_reg.s.pcterr) {
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/*
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* We are getting preamble errors at
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* 10Mbps. Most likely the PHY is
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* giving us packets with mis aligned
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* preambles. In order to get these
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* packets we need to disable preamble
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* checking and do it in software.
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*/
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cvm_oct_set_hw_preamble(priv, false);
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printk_ratelimited("%s: Using 10Mbps with software preamble removal\n",
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dev->name);
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}
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}
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if (use_global_register_lock)
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spin_unlock_irqrestore(&global_register_lock, flags);
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else
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mutex_unlock(&priv->phydev->bus->mdio_lock);
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return;
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}
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/* Since the 10Mbps preamble workaround is allowed we need to enable
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* preamble checking, FCS stripping, and clear error bits on
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* every speed change. If errors occur during 10Mbps operation
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* the above code will change this stuff
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*/
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cvm_oct_set_hw_preamble(priv, true);
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if (priv->phydev == NULL) {
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link_info = cvmx_helper_link_autoconf(priv->port);
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priv->link_info = link_info.u64;
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}
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if (use_global_register_lock)
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spin_unlock_irqrestore(&global_register_lock, flags);
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else
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mutex_unlock(&priv->phydev->bus->mdio_lock);
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if (priv->phydev == NULL) {
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/* Tell core. */
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if (link_info.s.link_up) {
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if (!netif_carrier_ok(dev))
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netif_carrier_on(dev);
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} else if (netif_carrier_ok(dev)) {
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netif_carrier_off(dev);
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}
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cvm_oct_note_carrier(priv, link_info);
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}
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}
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static int cmv_oct_rgmii_gmx_interrupt(int interface)
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{
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int index;
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int count = 0;
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/* Loop through every port of this interface */
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for (index = 0;
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index < cvmx_helper_ports_on_interface(interface);
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index++) {
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union cvmx_gmxx_rxx_int_reg gmx_rx_int_reg;
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/* Read the GMX interrupt status bits */
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gmx_rx_int_reg.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_REG
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(index, interface));
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gmx_rx_int_reg.u64 &= cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
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(index, interface));
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/* Poll the port if inband status changed */
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if (gmx_rx_int_reg.s.phy_dupx || gmx_rx_int_reg.s.phy_link ||
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gmx_rx_int_reg.s.phy_spd) {
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struct net_device *dev =
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cvm_oct_device[cvmx_helper_get_ipd_port
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(interface, index)];
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struct octeon_ethernet *priv = netdev_priv(dev);
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if (dev && !atomic_read(&cvm_oct_poll_queue_stopping))
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queue_work(cvm_oct_poll_queue,
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&priv->port_work);
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gmx_rx_int_reg.u64 = 0;
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gmx_rx_int_reg.s.phy_dupx = 1;
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gmx_rx_int_reg.s.phy_link = 1;
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gmx_rx_int_reg.s.phy_spd = 1;
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cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, interface),
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gmx_rx_int_reg.u64);
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count++;
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}
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}
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return count;
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}
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static irqreturn_t cvm_oct_rgmii_rml_interrupt(int cpl, void *dev_id)
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{
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union cvmx_npi_rsl_int_blocks rsl_int_blocks;
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int count = 0;
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rsl_int_blocks.u64 = cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS);
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/* Check and see if this interrupt was caused by the GMX0 block */
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if (rsl_int_blocks.s.gmx0)
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count += cmv_oct_rgmii_gmx_interrupt(0);
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/* Check and see if this interrupt was caused by the GMX1 block */
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if (rsl_int_blocks.s.gmx1)
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count += cmv_oct_rgmii_gmx_interrupt(1);
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return count ? IRQ_HANDLED : IRQ_NONE;
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}
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int cvm_oct_rgmii_open(struct net_device *dev)
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{
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return cvm_oct_common_open(dev, cvm_oct_rgmii_poll);
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}
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static void cvm_oct_rgmii_immediate_poll(struct work_struct *work)
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{
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struct octeon_ethernet *priv =
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container_of(work, struct octeon_ethernet, port_work);
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cvm_oct_rgmii_poll(cvm_oct_device[priv->port]);
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}
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int cvm_oct_rgmii_init(struct net_device *dev)
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{
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struct octeon_ethernet *priv = netdev_priv(dev);
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int r;
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cvm_oct_common_init(dev);
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INIT_WORK(&priv->port_work, cvm_oct_rgmii_immediate_poll);
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/*
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* Due to GMX errata in CN3XXX series chips, it is necessary
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* to take the link down immediately when the PHY changes
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* state. In order to do this we call the poll function every
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* time the RGMII inband status changes. This may cause
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* problems if the PHY doesn't implement inband status
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* properly.
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*/
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if (number_rgmii_ports == 0) {
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r = request_irq(OCTEON_IRQ_RML, cvm_oct_rgmii_rml_interrupt,
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IRQF_SHARED, "RGMII", &number_rgmii_ports);
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if (r != 0)
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return r;
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}
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number_rgmii_ports++;
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/*
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* Only true RGMII ports need to be polled. In GMII mode, port
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* 0 is really a RGMII port.
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*/
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if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
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&& (priv->port == 0))
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|| (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
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if (!octeon_is_simulation()) {
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union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
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int interface = INTERFACE(priv->port);
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int index = INDEX(priv->port);
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/*
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* Enable interrupts on inband status changes
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* for this port.
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*/
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gmx_rx_int_en.u64 = 0;
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gmx_rx_int_en.s.phy_dupx = 1;
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gmx_rx_int_en.s.phy_link = 1;
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gmx_rx_int_en.s.phy_spd = 1;
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cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface),
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gmx_rx_int_en.u64);
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}
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}
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return 0;
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}
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void cvm_oct_rgmii_uninit(struct net_device *dev)
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{
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struct octeon_ethernet *priv = netdev_priv(dev);
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cvm_oct_common_uninit(dev);
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/*
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* Only true RGMII ports need to be polled. In GMII mode, port
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* 0 is really a RGMII port.
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*/
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if (((priv->imode == CVMX_HELPER_INTERFACE_MODE_GMII)
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&& (priv->port == 0))
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|| (priv->imode == CVMX_HELPER_INTERFACE_MODE_RGMII)) {
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if (!octeon_is_simulation()) {
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union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
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int interface = INTERFACE(priv->port);
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int index = INDEX(priv->port);
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/*
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* Disable interrupts on inband status changes
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* for this port.
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*/
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gmx_rx_int_en.u64 =
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cvmx_read_csr(CVMX_GMXX_RXX_INT_EN
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(index, interface));
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gmx_rx_int_en.s.phy_dupx = 0;
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gmx_rx_int_en.s.phy_link = 0;
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gmx_rx_int_en.s.phy_spd = 0;
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cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, interface),
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gmx_rx_int_en.u64);
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}
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}
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/* Remove the interrupt handler when the last port is removed. */
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number_rgmii_ports--;
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if (number_rgmii_ports == 0)
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free_irq(OCTEON_IRQ_RML, &number_rgmii_ports);
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cancel_work_sync(&priv->port_work);
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}
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