linux/drivers/perf/hisilicon
Shaokun Zhang eb4f521325 drivers/perf: hisi: Fixup one DDRC PMU register offset
For DDRC PMU, each PMU counter is fixed-purpose. There is a mismatch
between perf list and driver definition on rw_chg event.
# perf list | grep chg
  hisi_sccl1_ddrc0/rnk_chg/                          [Kernel PMU event]
  hisi_sccl1_ddrc0/rw_chg/                           [Kernel PMU event]
But the register offset of rw_chg event is not defined in the driver,
meanwhile bnk_chg register offset is mis-defined, let's fixup it.

Fixes: 904dcf03f0 ("perf: hisi: Add support for HiSilicon SoC DDRC PMU driver")
Cc: stable@vger.kernel.org
Cc: John Garry <john.garry@huawei.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reported-by: Weijian Huang <huangweijian4@hisilicon.com>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2019-01-04 10:13:27 +00:00
..
Makefile perf: hisi: Add support for HiSilicon SoC DDRC PMU driver 2017-10-19 17:06:35 +01:00
hisi_uncore_ddrc_pmu.c drivers/perf: hisi: Fixup one DDRC PMU register offset 2019-01-04 10:13:27 +00:00
hisi_uncore_hha_pmu.c perf: hisi: Add support for HiSilicon SoC HHA PMU driver 2017-10-19 17:06:35 +01:00
hisi_uncore_l3c_pmu.c
hisi_uncore_pmu.c drivers/perf: hisi: update the sccl_id/ccl_id when MT is supported 2018-07-24 15:40:43 +01:00
hisi_uncore_pmu.h