134 lines
4.1 KiB
C
134 lines
4.1 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CPUTYPE_H
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#define __ASM_CPUTYPE_H
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#define INVALID_HWID ULONG_MAX
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#define MPIDR_UP_BITMASK (0x1 << 30)
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#define MPIDR_MT_BITMASK (0x1 << 24)
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#define MPIDR_HWID_BITMASK 0xff00ffffff
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#define MPIDR_LEVEL_BITS_SHIFT 3
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#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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#define MPIDR_LEVEL_SHIFT(level) \
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(((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
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#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
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((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
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#define MIDR_REVISION_MASK 0xf
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#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
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#define MIDR_PARTNUM_SHIFT 4
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#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
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#define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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#define MIDR_ARCHITECTURE_SHIFT 16
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#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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#define MIDR_VARIANT_SHIFT 20
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#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
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#define MIDR_VARIANT(midr) \
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(((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
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#define MIDR_IMPLEMENTOR_SHIFT 24
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#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_IMPLEMENTOR(midr) \
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(((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
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#define MIDR_CPU_MODEL(imp, partnum) \
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(((imp) << MIDR_IMPLEMENTOR_SHIFT) | \
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(0xf << MIDR_ARCHITECTURE_SHIFT) | \
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((partnum) << MIDR_PARTNUM_SHIFT))
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#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
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MIDR_ARCHITECTURE_MASK)
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#define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \
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({ \
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u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \
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u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \
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\
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_model == (model) && rv >= (rv_min) && rv <= (rv_max); \
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})
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#define ARM_CPU_IMP_ARM 0x41
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#define ARM_CPU_IMP_APM 0x50
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#define ARM_CPU_IMP_CAVIUM 0x43
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#define ARM_CPU_IMP_BRCM 0x42
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#define ARM_CPU_PART_AEM_V8 0xD0F
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#define ARM_CPU_PART_FOUNDATION 0xD00
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#define ARM_CPU_PART_CORTEX_A57 0xD07
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#define ARM_CPU_PART_CORTEX_A53 0xD03
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#define APM_CPU_PART_POTENZA 0x000
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#define CAVIUM_CPU_PART_THUNDERX 0x0A1
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#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
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#define BRCM_CPU_PART_VULCAN 0x516
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#ifndef __ASSEMBLY__
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#include <asm/sysreg.h>
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#define read_cpuid(reg) ({ \
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u64 __val; \
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asm("mrs_s %0, " __stringify(SYS_ ## reg) : "=r" (__val)); \
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__val; \
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})
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* rather than directly reading processor_id or read_cpuid() directly.
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*/
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static inline u32 __attribute_const__ read_cpuid_id(void)
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{
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return read_cpuid(MIDR_EL1);
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}
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static inline u64 __attribute_const__ read_cpuid_mpidr(void)
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{
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return read_cpuid(MPIDR_EL1);
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}
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static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
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{
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return MIDR_IMPLEMENTOR(read_cpuid_id());
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}
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static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
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{
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return MIDR_PARTNUM(read_cpuid_id());
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}
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static inline u32 __attribute_const__ read_cpuid_cachetype(void)
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{
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return read_cpuid(CTR_EL0);
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}
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#endif /* __ASSEMBLY__ */
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#endif
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