dc4fbba11e
The enable_kernel_*() functions leave the relevant MSR bits enabled until we exit the kernel sometime later. Create disable versions that wrap the kernel use of FP, Altivec VSX or SPE. While we don't want to disable it normally for performance reasons (MSR writes are slow), it will be used for a debug boot option that does this and catches bad uses in other areas of the kernel. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
130 lines
3.3 KiB
Ucode
130 lines
3.3 KiB
Ucode
/* -*- linux-c -*- ------------------------------------------------------- *
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*
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* Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, Inc., 53 Temple Place Ste 330,
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* Boston MA 02111-1307, USA; either version 2 of the License, or
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* (at your option) any later version; incorporated herein by reference.
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*
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* ----------------------------------------------------------------------- */
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/*
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* raid6altivec$#.c
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*
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* $#-way unrolled portable integer math RAID-6 instruction set
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*
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* This file is postprocessed using unroll.awk
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*
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* <benh> hpa: in process,
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* you can just "steal" the vec unit with enable_kernel_altivec() (but
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* bracked this with preempt_disable/enable or in a lock)
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*/
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#include <linux/raid/pq.h>
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#include <altivec.h>
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#ifdef __KERNEL__
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# include <asm/cputable.h>
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# include <asm/switch_to.h>
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/*
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* This is the C data type to use. We use a vector of
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* signed char so vec_cmpgt() will generate the right
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* instruction.
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*/
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typedef vector signed char unative_t;
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#define NBYTES(x) ((vector signed char) {x,x,x,x, x,x,x,x, x,x,x,x, x,x,x,x})
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#define NSIZE sizeof(unative_t)
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/*
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* The SHLBYTE() operation shifts each byte left by 1, *not*
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* rolling over into the next byte
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*/
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static inline __attribute_const__ unative_t SHLBYTE(unative_t v)
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{
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return vec_add(v,v);
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}
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/*
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* The MASK() operation returns 0xFF in any byte for which the high
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* bit is 1, 0x00 for any byte for which the high bit is 0.
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*/
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static inline __attribute_const__ unative_t MASK(unative_t v)
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{
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unative_t zv = NBYTES(0);
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/* vec_cmpgt returns a vector bool char; thus the need for the cast */
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return (unative_t)vec_cmpgt(zv, v);
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}
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/* This is noinline to make damned sure that gcc doesn't move any of the
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Altivec code around the enable/disable code */
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static void noinline
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raid6_altivec$#_gen_syndrome_real(int disks, size_t bytes, void **ptrs)
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{
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u8 **dptr = (u8 **)ptrs;
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u8 *p, *q;
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int d, z, z0;
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unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
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unative_t x1d = NBYTES(0x1d);
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z0 = disks - 3; /* Highest data disk */
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p = dptr[z0+1]; /* XOR parity */
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q = dptr[z0+2]; /* RS syndrome */
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for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
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wq$$ = wp$$ = *(unative_t *)&dptr[z0][d+$$*NSIZE];
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for ( z = z0-1 ; z >= 0 ; z-- ) {
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wd$$ = *(unative_t *)&dptr[z][d+$$*NSIZE];
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wp$$ = vec_xor(wp$$, wd$$);
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w2$$ = MASK(wq$$);
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w1$$ = SHLBYTE(wq$$);
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w2$$ = vec_and(w2$$, x1d);
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w1$$ = vec_xor(w1$$, w2$$);
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wq$$ = vec_xor(w1$$, wd$$);
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}
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*(unative_t *)&p[d+NSIZE*$$] = wp$$;
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*(unative_t *)&q[d+NSIZE*$$] = wq$$;
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}
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}
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static void raid6_altivec$#_gen_syndrome(int disks, size_t bytes, void **ptrs)
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{
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preempt_disable();
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enable_kernel_altivec();
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raid6_altivec$#_gen_syndrome_real(disks, bytes, ptrs);
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disable_kernel_altivec();
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preempt_enable();
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}
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int raid6_have_altivec(void);
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#if $# == 1
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int raid6_have_altivec(void)
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{
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/* This assumes either all CPUs have Altivec or none does */
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# ifdef __KERNEL__
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return cpu_has_feature(CPU_FTR_ALTIVEC);
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# else
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return 1;
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# endif
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}
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#endif
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const struct raid6_calls raid6_altivec$# = {
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raid6_altivec$#_gen_syndrome,
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NULL, /* XOR not yet implemented */
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raid6_have_altivec,
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"altivecx$#",
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0
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};
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#endif /* CONFIG_ALTIVEC */
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