49 lines
1.3 KiB
C
49 lines
1.3 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CACHETYPE_H
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#define __ASM_CACHETYPE_H
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#include <asm/cputype.h>
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#define CTR_L1IP_SHIFT 14
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#define CTR_L1IP_MASK 3
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#define ICACHE_POLICY_RESERVED 0
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#define ICACHE_POLICY_AIVIVT 1
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#define ICACHE_POLICY_VIPT 2
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#define ICACHE_POLICY_PIPT 3
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static inline u32 icache_policy(void)
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{
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return (read_cpuid_cachetype() >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK;
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}
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/*
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* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
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* permitted in the I-cache.
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*/
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static inline int icache_is_aliasing(void)
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{
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return icache_policy() != ICACHE_POLICY_PIPT;
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}
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static inline int icache_is_aivivt(void)
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{
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return icache_policy() == ICACHE_POLICY_AIVIVT;
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}
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#endif /* __ASM_CACHETYPE_H */
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