1e0c1ce00d
Commit 0fa1f0609a (ARM: Orion: Fix
Virtual/Physical mixup with watchdog) broke the Dove & MV78xx0
build. Although these two SoC don't use the watchdog, the shared
platform code still needs to build. Add the necessary defines.
Cc: stable@vger.kernel.org
Reported-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
37 lines
1009 B
C
37 lines
1009 B
C
/*
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* arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/mv78xx0.h>
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#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
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#define L2_WRITETHROUGH 0x00020000
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
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#define IRQ_CAUSE_ERR_OFF 0x0000
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#define IRQ_CAUSE_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0008
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#define IRQ_MASK_ERR_OFF 0x000c
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#define IRQ_MASK_LOW_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
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#endif
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