179 lines
4.7 KiB
ArmAsm
179 lines
4.7 KiB
ArmAsm
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*
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* Derived from book3s_interrupts.S, which is:
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* Copyright SUSE Linux Products GmbH 2009
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#include <asm/ppc_asm.h>
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#include <asm/kvm_asm.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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#include <asm/exception-64s.h>
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#include <asm/ppc-opcode.h>
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/*****************************************************************************
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* *
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* Guest entry / exit code that is in kernel module memory (vmalloc) *
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* *
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****************************************************************************/
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/* Registers:
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* none
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*/
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_GLOBAL(__kvmppc_vcore_entry)
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/* Write correct stack frame */
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mflr r0
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std r0,PPC_LR_STKOFF(r1)
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/* Save host state to the stack */
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stdu r1, -SWITCH_FRAME_SIZE(r1)
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/* Save non-volatile registers (r14 - r31) and CR */
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SAVE_NVGPRS(r1)
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mfcr r3
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std r3, _CCR(r1)
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/* Save host DSCR */
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BEGIN_FTR_SECTION
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mfspr r3, SPRN_DSCR
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std r3, HSTATE_DSCR(r13)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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BEGIN_FTR_SECTION
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/* Save host DABR */
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mfspr r3, SPRN_DABR
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std r3, HSTATE_DABR(r13)
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END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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/* Hard-disable interrupts */
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mfmsr r10
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std r10, HSTATE_HOST_MSR(r13)
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rldicl r10,r10,48,1
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rotldi r10,r10,16
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mtmsrd r10,1
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/* Save host PMU registers */
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li r3, 1
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sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
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mfspr r7, SPRN_MMCR0 /* save MMCR0 */
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mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
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mfspr r6, SPRN_MMCRA
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BEGIN_FTR_SECTION
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/* On P7, clear MMCRA in order to disable SDAR updates */
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li r5, 0
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mtspr SPRN_MMCRA, r5
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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isync
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ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
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lbz r5, LPPACA_PMCINUSE(r3)
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cmpwi r5, 0
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beq 31f /* skip if not */
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mfspr r5, SPRN_MMCR1
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std r7, HSTATE_MMCR(r13)
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std r5, HSTATE_MMCR + 8(r13)
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std r6, HSTATE_MMCR + 16(r13)
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mfspr r3, SPRN_PMC1
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mfspr r5, SPRN_PMC2
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mfspr r6, SPRN_PMC3
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mfspr r7, SPRN_PMC4
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mfspr r8, SPRN_PMC5
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mfspr r9, SPRN_PMC6
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BEGIN_FTR_SECTION
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mfspr r10, SPRN_PMC7
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mfspr r11, SPRN_PMC8
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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stw r3, HSTATE_PMC(r13)
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stw r5, HSTATE_PMC + 4(r13)
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stw r6, HSTATE_PMC + 8(r13)
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stw r7, HSTATE_PMC + 12(r13)
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stw r8, HSTATE_PMC + 16(r13)
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stw r9, HSTATE_PMC + 20(r13)
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BEGIN_FTR_SECTION
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stw r10, HSTATE_PMC + 24(r13)
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stw r11, HSTATE_PMC + 28(r13)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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31:
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/*
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* Put whatever is in the decrementer into the
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* hypervisor decrementer.
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*/
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mfspr r8,SPRN_DEC
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mftb r7
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mtspr SPRN_HDEC,r8
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extsw r8,r8
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add r8,r8,r7
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std r8,HSTATE_DECEXP(r13)
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#ifdef CONFIG_SMP
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/*
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* On PPC970, if the guest vcpu has an external interrupt pending,
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* send ourselves an IPI so as to interrupt the guest once it
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* enables interrupts. (It must have interrupts disabled,
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* otherwise we would already have delivered the interrupt.)
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*
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* XXX If this is a UP build, smp_send_reschedule is not available,
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* so the interrupt will be delayed until the next time the vcpu
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* enters the guest with interrupts enabled.
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*/
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BEGIN_FTR_SECTION
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ld r4, HSTATE_KVM_VCPU(r13)
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ld r0, VCPU_PENDING_EXC(r4)
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li r7, (1 << BOOK3S_IRQPRIO_EXTERNAL)
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oris r7, r7, (1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
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and. r0, r0, r7
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beq 32f
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lhz r3, PACAPACAINDEX(r13)
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bl smp_send_reschedule
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nop
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32:
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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#endif /* CONFIG_SMP */
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/* Jump to partition switch code */
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bl .kvmppc_hv_entry_trampoline
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nop
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/*
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* We return here in virtual mode after the guest exits
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* with something that we can't handle in real mode.
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* Interrupts are enabled again at this point.
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*/
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/*
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* Register usage at this point:
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*
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* R1 = host R1
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* R2 = host R2
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* R12 = exit handler id
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* R13 = PACA
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*/
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/* Restore non-volatile host registers (r14 - r31) and CR */
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REST_NVGPRS(r1)
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ld r4, _CCR(r1)
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mtcr r4
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addi r1, r1, SWITCH_FRAME_SIZE
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ld r0, PPC_LR_STKOFF(r1)
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mtlr r0
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blr
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