For DDRC PMU, each PMU counter is fixed-purpose. There is a mismatch
between perf list and driver definition on rw_chg event.
# perf list | grep chg
hisi_sccl1_ddrc0/rnk_chg/ [Kernel PMU event]
hisi_sccl1_ddrc0/rw_chg/ [Kernel PMU event]
But the register offset of rw_chg event is not defined in the driver,
meanwhile bnk_chg register offset is mis-defined, let's fixup it.
Fixes:
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.. | ||
Makefile | ||
hisi_uncore_ddrc_pmu.c | ||
hisi_uncore_hha_pmu.c | ||
hisi_uncore_l3c_pmu.c | ||
hisi_uncore_pmu.c | ||
hisi_uncore_pmu.h |