570727b552
Adding Haswell PCI device IDs for ioatdma and simplify the detection of certain Xeon CPUs that has alignment bugs so that modifications can be changed at a single place going forward. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Dan Williams <djbw@fb.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
239 lines
7.3 KiB
C
239 lines
7.3 KiB
C
/*
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* Intel I/OAT DMA Linux driver
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* Copyright(c) 2007 - 2009 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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/*
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* This driver supports an Intel I/OAT DMA engine, which does asynchronous
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* copy operations.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/dca.h>
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#include <linux/slab.h>
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#include "dma.h"
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#include "dma_v2.h"
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#include "registers.h"
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#include "hw.h"
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MODULE_VERSION(IOAT_DMA_VERSION);
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_AUTHOR("Intel Corporation");
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static struct pci_device_id ioat_pci_tbl[] = {
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/* I/OAT v1 platforms */
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_CNB) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SCNB) },
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{ PCI_VDEVICE(UNISYS, PCI_DEVICE_ID_UNISYS_DMA_DIRECTOR) },
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/* I/OAT v2 platforms */
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB) },
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/* I/OAT v3 platforms */
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG0) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG1) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG2) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG3) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG4) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG5) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG6) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_TBG7) },
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/* I/OAT v3.2 platforms */
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF0) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF1) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF2) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF3) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF4) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF5) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF6) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF7) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF8) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_JSF9) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB0) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB1) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB2) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB3) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB4) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB5) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB6) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB7) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB8) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB9) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB0) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB1) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB2) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB3) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB4) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB5) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB6) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB7) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB8) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_IVB9) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW0) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW1) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW2) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW3) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW4) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW5) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW6) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW7) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW8) },
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{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IOAT_HSW9) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, ioat_pci_tbl);
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static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
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static void ioat_remove(struct pci_dev *pdev);
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static int ioat_dca_enabled = 1;
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module_param(ioat_dca_enabled, int, 0644);
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MODULE_PARM_DESC(ioat_dca_enabled, "control support of dca service (default: 1)");
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struct kmem_cache *ioat2_cache;
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#define DRV_NAME "ioatdma"
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static struct pci_driver ioat_pci_driver = {
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.name = DRV_NAME,
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.id_table = ioat_pci_tbl,
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.probe = ioat_pci_probe,
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.remove = ioat_remove,
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};
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static struct ioatdma_device *
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alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase)
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{
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struct device *dev = &pdev->dev;
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struct ioatdma_device *d = devm_kzalloc(dev, sizeof(*d), GFP_KERNEL);
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if (!d)
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return NULL;
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d->pdev = pdev;
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d->reg_base = iobase;
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return d;
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}
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static int ioat_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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void __iomem * const *iomap;
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struct device *dev = &pdev->dev;
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struct ioatdma_device *device;
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int err;
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err = pcim_enable_device(pdev);
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if (err)
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return err;
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err = pcim_iomap_regions(pdev, 1 << IOAT_MMIO_BAR, DRV_NAME);
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if (err)
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return err;
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iomap = pcim_iomap_table(pdev);
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if (!iomap)
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return -ENOMEM;
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
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if (err)
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err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (err)
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return err;
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
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if (err)
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err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (err)
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return err;
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device = alloc_ioatdma(pdev, iomap[IOAT_MMIO_BAR]);
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if (!device)
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return -ENOMEM;
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pci_set_master(pdev);
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pci_set_drvdata(pdev, device);
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device->version = readb(device->reg_base + IOAT_VER_OFFSET);
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if (device->version == IOAT_VER_1_2)
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err = ioat1_dma_probe(device, ioat_dca_enabled);
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else if (device->version == IOAT_VER_2_0)
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err = ioat2_dma_probe(device, ioat_dca_enabled);
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else if (device->version >= IOAT_VER_3_0)
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err = ioat3_dma_probe(device, ioat_dca_enabled);
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else
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return -ENODEV;
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if (err) {
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dev_err(dev, "Intel(R) I/OAT DMA Engine init failed\n");
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return -ENODEV;
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}
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return 0;
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}
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static void ioat_remove(struct pci_dev *pdev)
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{
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struct ioatdma_device *device = pci_get_drvdata(pdev);
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if (!device)
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return;
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dev_err(&pdev->dev, "Removing dma and dca services\n");
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if (device->dca) {
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unregister_dca_provider(device->dca, &pdev->dev);
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free_dca_provider(device->dca);
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device->dca = NULL;
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}
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ioat_dma_remove(device);
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}
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static int __init ioat_init_module(void)
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{
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int err;
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pr_info("%s: Intel(R) QuickData Technology Driver %s\n",
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DRV_NAME, IOAT_DMA_VERSION);
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ioat2_cache = kmem_cache_create("ioat2", sizeof(struct ioat_ring_ent),
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0, SLAB_HWCACHE_ALIGN, NULL);
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if (!ioat2_cache)
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return -ENOMEM;
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err = pci_register_driver(&ioat_pci_driver);
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if (err)
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kmem_cache_destroy(ioat2_cache);
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return err;
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}
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module_init(ioat_init_module);
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static void __exit ioat_exit_module(void)
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{
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pci_unregister_driver(&ioat_pci_driver);
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kmem_cache_destroy(ioat2_cache);
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}
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module_exit(ioat_exit_module);
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