d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
84 lines
2.0 KiB
C
84 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* wm8974.h -- WM8974 Soc Audio driver
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*/
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#ifndef _WM8974_H
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#define _WM8974_H
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/* WM8974 register space */
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#define WM8974_RESET 0x0
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#define WM8974_POWER1 0x1
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#define WM8974_POWER2 0x2
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#define WM8974_POWER3 0x3
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#define WM8974_IFACE 0x4
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#define WM8974_COMP 0x5
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#define WM8974_CLOCK 0x6
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#define WM8974_ADD 0x7
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#define WM8974_GPIO 0x8
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#define WM8974_DAC 0xa
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#define WM8974_DACVOL 0xb
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#define WM8974_ADC 0xe
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#define WM8974_ADCVOL 0xf
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#define WM8974_EQ1 0x12
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#define WM8974_EQ2 0x13
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#define WM8974_EQ3 0x14
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#define WM8974_EQ4 0x15
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#define WM8974_EQ5 0x16
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#define WM8974_DACLIM1 0x18
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#define WM8974_DACLIM2 0x19
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#define WM8974_NOTCH1 0x1b
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#define WM8974_NOTCH2 0x1c
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#define WM8974_NOTCH3 0x1d
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#define WM8974_NOTCH4 0x1e
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#define WM8974_ALC1 0x20
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#define WM8974_ALC2 0x21
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#define WM8974_ALC3 0x22
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#define WM8974_NGATE 0x23
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#define WM8974_PLLN 0x24
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#define WM8974_PLLK1 0x25
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#define WM8974_PLLK2 0x26
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#define WM8974_PLLK3 0x27
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#define WM8974_ATTEN 0x28
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#define WM8974_INPUT 0x2c
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#define WM8974_INPPGA 0x2d
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#define WM8974_ADCBOOST 0x2f
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#define WM8974_OUTPUT 0x31
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#define WM8974_SPKMIX 0x32
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#define WM8974_SPKVOL 0x36
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#define WM8974_MONOMIX 0x38
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#define WM8974_CACHEREGNUM 57
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/* Clock divider Id's */
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#define WM8974_OPCLKDIV 0
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#define WM8974_MCLKDIV 1
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#define WM8974_BCLKDIV 2
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/* PLL Out dividers */
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#define WM8974_OPCLKDIV_1 (0 << 4)
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#define WM8974_OPCLKDIV_2 (1 << 4)
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#define WM8974_OPCLKDIV_3 (2 << 4)
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#define WM8974_OPCLKDIV_4 (3 << 4)
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/* BCLK clock dividers */
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#define WM8974_BCLKDIV_1 (0 << 2)
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#define WM8974_BCLKDIV_2 (1 << 2)
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#define WM8974_BCLKDIV_4 (2 << 2)
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#define WM8974_BCLKDIV_8 (3 << 2)
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#define WM8974_BCLKDIV_16 (4 << 2)
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#define WM8974_BCLKDIV_32 (5 << 2)
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/* MCLK clock dividers */
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#define WM8974_MCLKDIV_1 (0 << 5)
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#define WM8974_MCLKDIV_1_5 (1 << 5)
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#define WM8974_MCLKDIV_2 (2 << 5)
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#define WM8974_MCLKDIV_3 (3 << 5)
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#define WM8974_MCLKDIV_4 (4 << 5)
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#define WM8974_MCLKDIV_6 (5 << 5)
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#define WM8974_MCLKDIV_8 (6 << 5)
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#define WM8974_MCLKDIV_12 (7 << 5)
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#endif
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