159 lines
3.5 KiB
C
159 lines
3.5 KiB
C
/* PIIX4 southbridge configuration registers */
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#ifndef _SOUTHBRIDGE_H_
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#define _SOUTHBRIDGE_H_
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#include <asm/head.h>
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#include <asm/mas.h>
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#include <asm/e2k_api.h>
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#include "../boot_io.h"
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extern int SB_bus, SB_device, SB_function;
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#if 0
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#define PCI_BUS 0
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#define PHYS_DEV 7
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#else
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#define PCI_BUS SB_bus
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#define PHYS_DEV SB_device
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#endif
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/* Nothbridge addr i/o ports 0xcf8 - 0xcfb */
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#define SB_IO_ADDR_BASE 0x0CF8
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#define SB_IO_ADDR_PORT0 0x0CF8
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#define SB_IO_ADDR_PORT1 0x0CF9
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#define SB_IO_ADDR_PORT2 0x0CFA
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#define SB_IO_ADDR_PORT3 0x0CFB
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/* Nothbridge data i/o ports 0xcfc - 0xcff */
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#define SB_IO_DATA_BASE 0x0CFC
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#define SB_IO_DATA_PORT0 0x0CFC
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#define SB_IO_DATA_PORT1 0x0CFD
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#define SB_IO_DATA_PORT2 0x0CFE
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#define SB_IO_DATA_PORT3 0x0CFF
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#define pci_cfg_xaddr(bus,physdev,fun,byte) \
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((byte&~3)|(fun<<8)|(physdev<<11)|(bus<<16)|(1<<31))
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#define data_port PHYS_X86_IO_BASE + SB_IO_DATA_BASE
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#define addr_port PHYS_X86_IO_BASE + SB_IO_ADDR_BASE
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static inline unsigned int SB_read_config(int reg, int func, int size)
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{
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unsigned int xaddr;
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int mask = reg & 0x3;
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int rval = 0;
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int cnt = 0;
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xaddr = pci_cfg_xaddr(PCI_BUS, PHYS_DEV, func, reg);
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NATIVE_WRITE_MAS_W(addr_port, xaddr, MAS_IOADDR);
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while (mask) {
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rval |= (NATIVE_READ_MAS_B(data_port + mask,
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MAS_IOADDR) << (cnt * 8));
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if (!--size)
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break;
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++mask;
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++cnt;
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if (mask == 4) {
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xaddr = pci_cfg_xaddr(PCI_BUS, PHYS_DEV,
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func, (reg + 4));
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NATIVE_WRITE_MAS_W(addr_port, xaddr, MAS_IOADDR);
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mask = 0;
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break;
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}
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}
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while (size & (reg & 0x3)) {
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rval |= (NATIVE_READ_MAS_B(data_port + mask,
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MAS_IOADDR) << (cnt * 8));
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if (!--size)
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break;
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++mask;
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++cnt;
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}
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switch (size) {
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case 0:
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break;
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case 1:
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rval = NATIVE_READ_MAS_B(data_port, MAS_IOADDR);
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break;
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case 2:
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rval = NATIVE_READ_MAS_H(data_port, MAS_IOADDR);
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break;
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case 4:
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rval = NATIVE_READ_MAS_W(data_port, MAS_IOADDR);
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break;
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default:
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break;
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}
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return rval;
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}
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#define SB_read_config8(reg, func) \
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((char)SB_read_config(reg, func, sizeof(char)))
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#define SB_read_config16(reg, func) \
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((short)SB_read_config(reg, func, sizeof(short)))
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#define SB_read_config32(reg, func) \
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((int)SB_read_config(reg, func, sizeof(int)))
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static inline void SB_write_config(int xdata, int reg, int func, int size)
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{
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unsigned int xaddr;
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int mask = reg & 0x3;
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int data;
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int cnt = 0;
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xaddr = pci_cfg_xaddr(PCI_BUS, PHYS_DEV, func, reg);
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NATIVE_WRITE_MAS_W(addr_port, xaddr, MAS_IOADDR);
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while (mask) {
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data = xdata >> (8 * cnt);
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NATIVE_WRITE_MAS_B(data_port + mask, data, MAS_IOADDR);
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if (!--size)
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break;
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++mask;
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++cnt;
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if (mask == 4) {
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xaddr = pci_cfg_xaddr(PCI_BUS, PHYS_DEV,
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func, (reg + 4));
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NATIVE_WRITE_MAS_W(addr_port, xaddr, MAS_IOADDR);
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mask = 0;
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break;
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}
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}
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while (size & (reg & 0x3)) {
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data = xdata >> (8 * cnt);
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NATIVE_WRITE_MAS_B(data_port + mask, data, MAS_IOADDR);
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if (!--size)
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break;
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++mask;
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++cnt;
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}
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switch (size) {
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case 0:
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break;
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case 1:
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NATIVE_WRITE_MAS_B(data_port, xdata, MAS_IOADDR);
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break;
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case 2:
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NATIVE_WRITE_MAS_H(data_port, xdata, MAS_IOADDR);
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break;
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case 4:
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NATIVE_WRITE_MAS_W(data_port, xdata, MAS_IOADDR);
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break;
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default:
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break;
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}
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}
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#define SB_write_config8(xdata, reg, func) \
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SB_write_config(xdata, reg, func, sizeof(char))
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#define SB_write_config16(xdata, reg, func) \
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SB_write_config(xdata, reg, func, sizeof(short))
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#define SB_write_config32(xdata, reg, func) \
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SB_write_config(xdata, reg, func, sizeof(int))
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#endif /* _SOUTHBRIDGE_H_ */
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