151 lines
4.1 KiB
C
151 lines
4.1 KiB
C
/*
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* CEPIC handling
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <asm/atomic.h>
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#include <asm/head.h>
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#include <asm/epic.h>
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#include <asm/bootinfo.h>
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#include <asm/e2k_debug.h>
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#include <asm/e2k_api.h>
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#include "boot_io.h"
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#include "pic.h"
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/**************************** DEBUG DEFINES *****************************/
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#undef DEBUG_BOOT_MODE
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#undef Dprintk
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#define DEBUG_BOOT_MODE 1 /* SMP CPU boot */
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#define Dprintk(fmt, ...) \
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do { \
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if (DEBUG_BOOT_MODE) \
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rom_printk(fmt, ##__VA_ARGS__); \
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} while (0)
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/************************************************************************/
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/*
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* Print all CEPIC/PREPIC registers
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*/
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void boot_print_cepic(void)
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{
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unsigned int value;
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value = native_epic_read_w(CEPIC_CTRL);
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rom_printk("0xfee00000 = CEPIC_CTRL: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_ID);
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rom_printk("0xfee00010 = CEPIC_ID: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_CPR);
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rom_printk("0xfee00070 = CEPIC_CPR: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_ESR);
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rom_printk("0xfee00080 = CEPIC_ESR: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_ESR2);
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rom_printk("0xfee00090 = CEPIC_ESR2: 0x%x\n", value);
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/* CEPIC_EOI is write-only */
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value = native_epic_read_w(CEPIC_CIR);
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rom_printk("0xfee000b0 = CEPIC_CIR: 0x%x\n", value);
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/* Reading CEPIC_PNMIRR starts NMI handling */
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value = native_epic_read_w(CEPIC_ICR);
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rom_printk("0xfee00200 = CEPIC_ICR: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_ICR2);
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rom_printk("0xfee00204 = CEPIC_ICR2: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_TIMER_LVTT);
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rom_printk("0xfee00220 = CEPIC_TIMER_LVTT: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_TIMER_INIT);
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rom_printk("0xfee00230 = CEPIC_TIMER_INIT: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_TIMER_CUR);
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rom_printk("0xfee00240 = CEPIC_TIMER_CUR: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_TIMER_DIV);
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rom_printk("0xfee00250 = CEPIC_TIMER_DIV: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_NM_TIMER_LVTT);
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rom_printk("0xfee00260 = CEPIC_NM_TIMER_LVTT: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_NM_TIMER_INIT);
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rom_printk("0xfee00270 = CEPIC_NM_TIMER_INIT: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_NM_TIMER_CUR);
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rom_printk("0xfee00280 = CEPIC_NM_TIMER_CUR: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_NM_TIMER_DIV);
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rom_printk("0xfee00290 = CEPIC_NM_TIMER_DIV: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_SVR);
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rom_printk("0xfee002a0 = CEPIC_SVR: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_PNMIRR_MASK);
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rom_printk("0xfee002d0 = CEPIC_PNMIRR_MASK: 0x%x\n", value);
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/* Reading CEPIC_VECT_INTA starts MI handling */
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value = native_epic_read_w(CEPIC_CTRL2);
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rom_printk("0xfee01820 = CEPIC_CTRL2: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_DAT);
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rom_printk("0xfee01830 = CEPIC_DAT: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_DAT2);
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rom_printk("0xfee01834 = CEPIC_DAT2: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_EPIC_INT);
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rom_printk("0xfee01850 = CEPIC_EPIC_INT: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_EPIC_INT2);
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rom_printk("0xfee01860 = CEPIC_EPIC_INT2: 0x%x\n", value);
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value = native_epic_read_w(CEPIC_EPIC_INT3);
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rom_printk("0xfee01864 = CEPIC_EPIC_INT3: 0x%x\n", value);
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rom_printk("\n");
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}
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/*
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* Placeholder for boot-time CEPIC setup. Currently reset state is fine for
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* kernel, so do nothing
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*/
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void boot_setup_cepic(int cpu)
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{
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}
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/*
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* Ensure that AP core received startup interrupt with matching address.
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* Print error messages, if that is not the case.
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*/
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void debug_epic_startup(int cpu, unsigned int value, unsigned long startup_addr)
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{
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unsigned long addr;
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Dprintk("CPU #%d : CEPIC_PNMIRR value = 0x%x\n", cpu, value);
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if (!(value & CEPIC_PNMIRR_STARTUP))
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rom_printk("CPU #%d : ERROR: CEPIC startup bit is not set\n",
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cpu);
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addr = value & CEPIC_PNMIRR_STARTUP_ENTRY;
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Dprintk("CPU #%d : CEPIC received STARTUP with addr 0x%x\n", cpu, addr);
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if (addr != startup_addr >> 12)
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rom_printk("CPU #%d : ERROR : CEPIC incorrect startup addr\n",
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cpu);
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}
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