212 lines
4.8 KiB
C
212 lines
4.8 KiB
C
#ifndef __BOOT_PIC_H
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#define __BOOT_PIC_H
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/*
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* Statically choose between APIC and EPIC basic functions, based on
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* CONFIG_BOOT_EPIC (defined in arch/e2k/boot/Makefile)
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*/
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#include <asm/apic.h>
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#include <asm/epic.h>
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#include "bios/printk.h"
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#include <asm/e2k_sic.h>
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#include "e2k_sic.h"
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#include <asm/sic_regs.h>
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/* Boot */
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#ifdef CONFIG_SMP
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extern unsigned int all_pic_ids[];
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#endif
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static inline void native_epic_write_w(unsigned int reg, unsigned int v)
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{
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NATIVE_WRITE_MAS_W(EPIC_DEFAULT_PHYS_BASE + reg, v, MAS_IOADDR);
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}
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static inline unsigned int native_epic_read_w(unsigned int reg)
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{
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return NATIVE_READ_MAS_W(EPIC_DEFAULT_PHYS_BASE + reg, MAS_IOADDR);
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}
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static inline void native_epic_write_d(unsigned int reg, unsigned long v)
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{
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NATIVE_WRITE_MAS_D(EPIC_DEFAULT_PHYS_BASE + reg, v, MAS_IOADDR);
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}
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static inline unsigned long native_epic_read_d(unsigned int reg)
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{
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return NATIVE_READ_MAS_D(EPIC_DEFAULT_PHYS_BASE + reg, MAS_IOADDR);
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}
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static inline void native_apic_write(unsigned int reg, unsigned int v)
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{
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NATIVE_WRITE_MAS_W(APIC_DEFAULT_PHYS_BASE + reg, v, MAS_IOADDR);
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}
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static inline unsigned int native_apic_read(unsigned int reg)
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{
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return NATIVE_READ_MAS_W(APIC_DEFAULT_PHYS_BASE + reg, MAS_IOADDR);
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}
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#ifdef CONFIG_BOOT_EPIC
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#define PIC_DEFAULT_PHYS_BASE EPIC_DEFAULT_PHYS_BASE
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#define IO_PIC_DEFAULT_PHYS_BASE IO_EPIC_DEFAULT_PHYS_BASE
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extern void debug_epic_startup(int cpu, unsigned int value, unsigned long addr);
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static inline void debug_pic_startup(int cpu, unsigned int value,
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unsigned long addr)
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{
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debug_epic_startup(cpu, value, addr);
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}
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extern void boot_setup_cepic(int cpu);
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static inline void setup_local_pic(int cpu)
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{
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boot_setup_cepic(cpu);
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}
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extern void boot_print_cepic(void);
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static inline void print_local_pic(void)
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{
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boot_print_cepic();
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}
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#define NATIVE_READ_PIC_ID() native_read_epic_id()
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static inline unsigned int native_read_epic_id(void)
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{
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return cepic_id_full_to_short(native_epic_read_w(CEPIC_ID));
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}
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/* No need for EOI at boot-time */
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#define native_pic_write_eoi() do {} while (0)
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static inline unsigned int native_pic_read_esr(void)
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{
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return native_epic_read_w(CEPIC_ESR) & CEPIC_ESR_BIT_MASK;
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}
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static inline unsigned int native_pic_read_icr_busy(void)
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{
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union cepic_icr reg;
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reg.raw = (unsigned long)native_epic_read_w(CEPIC_ICR);
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return reg.bits.stat;
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}
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static inline void native_pic_reset_esr(void)
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{
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native_epic_write_w(CEPIC_ESR, 0);
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}
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static inline void native_pic_send_startup(int picid, unsigned long addr)
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{
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union cepic_icr icr;
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/* Send startup IPI via ICR */
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icr.raw = 0;
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icr.bits.dst = cepic_id_short_to_full(picid);
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icr.bits.dlvm = CEPIC_ICR_DLVM_STARTUP;
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icr.bits.vect = addr >> 12;
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native_epic_write_d(CEPIC_ICR, icr.raw);
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}
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static inline unsigned int native_pic_read_nm(void)
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{
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return native_epic_read_w(CEPIC_PNMIRR);
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}
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static inline void native_pic_reset_nm(void)
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{
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native_epic_write_w(CEPIC_PNMIRR, CEPIC_PNMIRR_BIT_MASK);
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}
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static inline unsigned int native_pic_read_version(void)
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{
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return NATIVE_GET_SICREG(prepic_version, 0, 0);
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}
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#else /* CONFIG_BOOT_EPIC */
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#define PIC_DEFAULT_PHYS_BASE APIC_DEFAULT_PHYS_BASE
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#define IO_PIC_DEFAULT_PHYS_BASE IO_APIC_DEFAULT_PHYS_BASE
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#define NATIVE_READ_PIC_ID() native_read_apic_id()
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static inline unsigned int native_read_apic_id(void)
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{
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return GET_APIC_ID(native_apic_read(APIC_ID));
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}
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extern void debug_apic_startup(int cpu, unsigned int value, unsigned long addr);
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static inline void debug_pic_startup(int cpu, unsigned int value,
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unsigned long addr)
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{
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debug_apic_startup(cpu, value, addr);
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}
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extern void setup_local_apic(int cpu);
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static inline void setup_local_pic(int cpu)
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{
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setup_local_apic(cpu);
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}
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extern void print_local_apic(void);
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static inline void print_local_pic(void)
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{
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print_local_apic();
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}
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static inline unsigned int native_pic_read_esr(void)
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{
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return native_apic_read(APIC_ESR) & 0xEF;
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}
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static inline unsigned int native_pic_read_icr_busy(void)
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{
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return native_apic_read(APIC_ICR) & APIC_ICR_BUSY;
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}
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static inline void native_pic_reset_esr(void)
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{
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native_apic_write(APIC_ESR, 0);
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}
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static inline void native_pic_send_startup(int picid, unsigned long addr)
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{
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/* Target chip */
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native_apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(picid));
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/* Boot on the stack */
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/* Kick the second */
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native_apic_write(APIC_ICR, APIC_DM_STARTUP
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| (addr >> 12));
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}
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static inline unsigned int native_pic_read_nm(void)
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{
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return native_apic_read(APIC_NM);
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}
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static inline void native_pic_reset_nm(void)
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{
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native_apic_write(APIC_NM, APIC_NM_BIT_MASK);
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}
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static inline void native_pic_write_eoi(void)
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{
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native_apic_write(APIC_EOI, 0x0);
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}
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static inline unsigned int native_pic_read_version(void)
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{
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unsigned int apic_version;
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apic_version = GET_APIC_VERSION(native_apic_read(APIC_LVR));
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if (apic_version == 0)
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apic_version = APIC_VERSION;
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return apic_version;
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}
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#endif /* CONFIG_BOOT_EPIC */
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#endif /* __BOOT_PIC_H */
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