1ce447b90f
970 and Power4 don't support "continuous sampling" which means that when we aren't in marked instruction sampling mode (marked events), SIAR isn't updated with the last instruction sampled before the perf interrupt. On those processors, we must thus use the exception SRR0 value as the sampled instruction pointer. Those processors also don't support the SIPR and SIHV bits in MMCRA which means we need some kind of heuristic to decide if SIAR values represent kernel or user addresses. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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| .. | ||
| Makefile | ||
| callchain.c | ||
| core-book3s.c | ||
| core-fsl-emb.c | ||
| e500-pmu.c | ||
| mpc7450-pmu.c | ||
| power4-pmu.c | ||
| power5+-pmu.c | ||
| power5-pmu.c | ||
| power6-pmu.c | ||
| power7-pmu.c | ||
| ppc970-pmu.c | ||