Max Filippov 34a57be0f9 xtensa: fix xtensa_wsr always writing 0 ... commit a3d0245c58f962ee99d4440ea0eaf45fb7f5a5cc upstream. The commit cad6fade6e ("xtensa: clean up WSR*/RSR*/get_sr/set_sr") replaced 'WSR' macro in the function xtensa_wsr with 'xtensa_set_sr', but variable 'v' in the xtensa_set_sr body shadowed the argument 'v' passed to it, resulting in wrong value written to debug registers. Fix that by removing intermediate variable from the xtensa_set_sr macro body. Cc: stable@vger.kernel.org Fixes: cad6fade6e ("xtensa: clean up WSR*/RSR*/get_sr/set_sr") Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2022-04-15 14:18:03 +02:00
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asm	xtensa: fix xtensa_wsr always writing 0	2022-04-15 14:18:03 +02:00
uapi/asm	mm: introduce MADV_PAGEOUT	2019-09-25 17:51:41 -07:00