393 lines
15 KiB
Plaintext
393 lines
15 KiB
Plaintext
STMicroelectronics 10/100/1000 Synopsys Ethernet driver
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Copyright (C) 2007-2015 STMicroelectronics Ltd
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
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(Synopsys IP blocks).
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Currently this network device driver is for all STi embedded MAC/GMAC
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(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
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FF1152AMT0221 D1215994A VIRTEX FPGA board.
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DWC Ether MAC 10/100/1000 Universal version 3.70a (and older) and DWC Ether
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MAC 10/100 Universal version 4.0 have been used for developing this driver.
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This driver supports both the platform bus and PCI.
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Please, for more information also visit: www.stlinux.com
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1) Kernel Configuration
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The kernel configuration option is STMMAC_ETH:
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Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) --->
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STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH)
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CONFIG_STMMAC_PLATFORM: is to enable the platform driver.
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CONFIG_STMMAC_PCI: is to enable the pci driver.
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2) Driver parameters list:
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debug: message level (0: no output, 16: all);
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phyaddr: to manually provide the physical address to the PHY device;
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dma_rxsize: DMA rx ring size;
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dma_txsize: DMA tx ring size;
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buf_sz: DMA buffer size;
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tc: control the HW FIFO threshold;
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watchdog: transmit timeout (in milliseconds);
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flow_ctrl: Flow control ability [on/off];
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pause: Flow Control Pause Time;
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eee_timer: tx EEE timer;
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chain_mode: select chain mode instead of ring.
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3) Command line options
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Driver parameters can be also passed in command line by using:
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stmmaceth=dma_rxsize:128,dma_txsize:512
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4) Driver information and notes
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4.1) Transmit process
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The xmit method is invoked when the kernel needs to transmit a packet; it sets
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the descriptors in the ring and informs the DMA engine that there is a packet
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ready to be transmitted.
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By default, the driver sets the NETIF_F_SG bit in the features field of the
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net_device structure enabling the scatter-gather feature. This is true on
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chips and configurations where the checksum can be done in hardware.
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Once the controller has finished transmitting the packet, napi will be
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scheduled to release the transmit resources.
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4.2) Receive process
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When one or more packets are received, an interrupt happens. The interrupts
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are not queued so the driver has to scan all the descriptors in the ring during
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the receive process.
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This is based on NAPI so the interrupt handler signals only if there is work
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to be done, and it exits.
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Then the poll method will be scheduled at some future point.
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The incoming packets are stored, by the DMA, in a list of pre-allocated socket
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buffers in order to avoid the memcpy (zero-copy).
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4.3) Interrupt Mitigation
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The driver is able to mitigate the number of its DMA interrupts
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using NAPI for the reception on chips older than the 3.50.
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New chips have an HW RX-Watchdog used for this mitigation.
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Mitigation parameters can be tuned by ethtool.
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4.4) WOL
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Wake up on Lan feature through Magic and Unicast frames are supported for the
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GMAC core.
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4.5) DMA descriptors
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Driver handles both normal and alternate descriptors. The latter has been only
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tested on DWC Ether MAC 10/100/1000 Universal version 3.41a and later.
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STMMAC supports DMA descriptor to operate both in dual buffer (RING)
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and linked-list(CHAINED) mode. In RING each descriptor points to two
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data buffer pointers whereas in CHAINED mode they point to only one data
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buffer pointer. RING mode is the default.
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In CHAINED mode each descriptor will have pointer to next descriptor in
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the list, hence creating the explicit chaining in the descriptor itself,
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whereas such explicit chaining is not possible in RING mode.
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4.5.1) Extended descriptors
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The extended descriptors give us information about the Ethernet payload
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when it is carrying PTP packets or TCP/UDP/ICMP over IP.
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These are not available on GMAC Synopsys chips older than the 3.50.
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At probe time the driver will decide if these can be actually used.
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This support also is mandatory for PTPv2 because the extra descriptors
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are used for saving the hardware timestamps and Extended Status.
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4.6) Ethtool support
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Ethtool is supported.
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For example, driver statistics (including RMON), internal errors can be taken
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using:
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# ethtool -S ethX command
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4.7) Jumbo and Segmentation Offloading
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Jumbo frames are supported and tested for the GMAC.
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The GSO has been also added but it's performed in software.
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LRO is not supported.
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4.8) Physical
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The driver is compatible with Physical Abstraction Layer to be connected with
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PHY and GPHY devices.
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4.9) Platform information
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Several information can be passed through the platform and device-tree.
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struct plat_stmmacenet_data {
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char *phy_bus_name;
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int bus_id;
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int phy_addr;
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int interface;
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struct stmmac_mdio_bus_data *mdio_bus_data;
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struct stmmac_dma_cfg *dma_cfg;
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int clk_csr;
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int has_gmac;
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int enh_desc;
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int tx_coe;
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int rx_coe;
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int bugged_jumbo;
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int pmt;
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int force_sf_dma_mode;
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int force_thresh_dma_mode;
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int riwt_off;
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int max_speed;
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int maxmtu;
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void (*fix_mac_speed)(void *priv, unsigned int speed);
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void (*bus_setup)(void __iomem *ioaddr);
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int (*init)(struct platform_device *pdev, void *priv);
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void (*exit)(struct platform_device *pdev, void *priv);
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void *bsp_priv;
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int has_gmac4;
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bool tso_en;
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};
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Where:
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o phy_bus_name: phy bus name to attach to the stmmac.
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o bus_id: bus identifier.
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o phy_addr: the physical address can be passed from the platform.
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If it is set to -1 the driver will automatically
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detect it at run-time by probing all the 32 addresses.
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o interface: PHY device's interface.
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o mdio_bus_data: specific platform fields for the MDIO bus.
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o dma_cfg: internal DMA parameters
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o pbl: the Programmable Burst Length is maximum number of beats to
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be transferred in one DMA transaction.
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GMAC also enables the 4xPBL by default.
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o fixed_burst/mixed_burst/burst_len
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o clk_csr: fixed CSR Clock range selection.
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o has_gmac: uses the GMAC core.
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o enh_desc: if sets the MAC will use the enhanced descriptor structure.
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o tx_coe: core is able to perform the tx csum in HW.
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o rx_coe: the supports three check sum offloading engine types:
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type_1, type_2 (full csum) and no RX coe.
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o bugged_jumbo: some HWs are not able to perform the csum in HW for
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over-sized frames due to limited buffer sizes.
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Setting this flag the csum will be done in SW on
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JUMBO frames.
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o pmt: core has the embedded power module (optional).
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o force_sf_dma_mode: force DMA to use the Store and Forward mode
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instead of the Threshold.
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o force_thresh_dma_mode: force DMA to use the Threshold mode other than
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the Store and Forward mode.
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o riwt_off: force to disable the RX watchdog feature and switch to NAPI mode.
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o fix_mac_speed: this callback is used for modifying some syscfg registers
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(on ST SoCs) according to the link speed negotiated by the
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physical layer .
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o bus_setup: perform HW setup of the bus. For example, on some ST platforms
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this field is used to configure the AMBA bridge to generate more
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efficient STBus traffic.
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o init/exit: callbacks used for calling a custom initialization;
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this is sometime necessary on some platforms (e.g. ST boxes)
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where the HW needs to have set some PIO lines or system cfg
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registers. init/exit callbacks should not use or modify
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platform data.
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o bsp_priv: another private pointer.
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o has_gmac4: uses GMAC4 core.
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o tso_en: Enables TSO (TCP Segmentation Offload) feature.
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For MDIO bus The we have:
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struct stmmac_mdio_bus_data {
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int (*phy_reset)(void *priv);
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unsigned int phy_mask;
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int *irqs;
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int probed_phy_irq;
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};
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Where:
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o phy_reset: hook to reset the phy device attached to the bus.
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o phy_mask: phy mask passed when register the MDIO bus within the driver.
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o irqs: list of IRQs, one per PHY.
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o probed_phy_irq: if irqs is NULL, use this for probed PHY.
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For DMA engine we have the following internal fields that should be
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tuned according to the HW capabilities.
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struct stmmac_dma_cfg {
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int pbl;
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int fixed_burst;
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int burst_len_supported;
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};
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Where:
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o pbl: Programmable Burst Length
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o fixed_burst: program the DMA to use the fixed burst mode
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o burst_len: this is the value we put in the register
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supported values are provided as macros in
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linux/stmmac.h header file.
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---
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Below an example how the structures above are using on ST platforms.
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static struct plat_stmmacenet_data stxYYY_ethernet_platform_data = {
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.has_gmac = 0,
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.enh_desc = 0,
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.fix_mac_speed = stxYYY_ethernet_fix_mac_speed,
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|-> to write an internal syscfg
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| on this platform when the
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| link speed changes from 10 to
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| 100 and viceversa
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.init = &stmmac_claim_resource,
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|-> On ST SoC this calls own "PAD"
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| manager framework to claim
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| all the resources necessary
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| (GPIO ...). The .custom_cfg field
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| is used to pass a custom config.
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};
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Below the usage of the stmmac_mdio_bus_data: on this SoC, in fact,
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there are two MAC cores: one MAC is for MDIO Bus/PHY emulation
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with fixed_link support.
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static struct stmmac_mdio_bus_data stmmac1_mdio_bus = {
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.phy_reset = phy_reset;
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|-> function to provide the phy_reset on this board
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.phy_mask = 0,
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};
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static struct fixed_phy_status stmmac0_fixed_phy_status = {
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.link = 1,
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.speed = 100,
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.duplex = 1,
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};
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During the board's device_init we can configure the first
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MAC for fixed_link by calling:
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fixed_phy_add(PHY_POLL, 1, &stmmac0_fixed_phy_status, -1);
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and the second one, with a real PHY device attached to the bus,
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by using the stmmac_mdio_bus_data structure (to provide the id, the
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reset procedure etc).
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Note that, starting from new chips, where it is available the HW capability
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register, many configurations are discovered at run-time for example to
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understand if EEE, HW csum, PTP, enhanced descriptor etc are actually
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available. As strategy adopted in this driver, the information from the HW
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capability register can replace what has been passed from the platform.
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4.10) Device-tree support.
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Please see the following document:
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Documentation/devicetree/bindings/net/stmmac.txt
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4.11) This is a summary of the content of some relevant files:
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o stmmac_main.c: to implement the main network device driver;
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o stmmac_mdio.c: to provide mdio functions;
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o stmmac_pci: this the PCI driver;
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o stmmac_platform.c: this the platform driver (OF supported)
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o stmmac_ethtool.c: to implement the ethtool support;
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o stmmac.h: private driver structure;
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o common.h: common definitions and VFTs;
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o mmc_core.c/mmc.h: Management MAC Counters;
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o stmmac_hwtstamp.c: HW timestamp support for PTP;
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o stmmac_ptp.c: PTP 1588 clock;
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o stmmac_pcs.h: Physical Coding Sublayer common implementation;
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o dwmac-<XXX>.c: these are for the platform glue-logic file; e.g. dwmac-sti.c
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for STMicroelectronics SoCs.
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- GMAC 3.x
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o descs.h: descriptor structure definitions;
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o dwmac1000_core.c: dwmac GiGa core functions;
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o dwmac1000_dma.c: dma functions for the GMAC chip;
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o dwmac1000.h: specific header file for the dwmac GiGa;
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o dwmac100_core: dwmac 100 core code;
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o dwmac100_dma.c: dma functions for the dwmac 100 chip;
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o dwmac1000.h: specific header file for the MAC;
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o dwmac_lib.c: generic DMA functions;
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o enh_desc.c: functions for handling enhanced descriptors;
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o norm_desc.c: functions for handling normal descriptors;
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o chain_mode.c/ring_mode.c:: functions to manage RING/CHAINED modes;
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- GMAC4.x generation
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o dwmac4_core.c: dwmac GMAC4.x core functions;
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o dwmac4_desc.c: functions for handling GMAC4.x descriptors;
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o dwmac4_descs.h: descriptor definitions;
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o dwmac4_dma.c: dma functions for the GMAC4.x chip;
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o dwmac4_dma.h: dma definitions for the GMAC4.x chip;
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o dwmac4.h: core definitions for the GMAC4.x chip;
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o dwmac4_lib.c: generic GMAC4.x functions;
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4.12) TSO support (GMAC4.x)
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TSO (Tcp Segmentation Offload) feature is supported by GMAC 4.x chip family.
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When a packet is sent through TCP protocol, the TCP stack ensures that
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the SKB provided to the low level driver (stmmac in our case) matches with
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the maximum frame len (IP header + TCP header + payload <= 1500 bytes (for
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MTU set to 1500)). It means that if an application using TCP want to send a
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packet which will have a length (after adding headers) > 1514 the packet
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will be split in several TCP packets: The data payload is split and headers
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(TCP/IP ..) are added. It is done by software.
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When TSO is enabled, the TCP stack doesn't care about the maximum frame
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length and provide SKB packet to stmmac as it is. The GMAC IP will have to
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perform the segmentation by it self to match with maximum frame length.
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This feature can be enabled in device tree through "snps,tso" entry.
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5) Debug Information
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The driver exports many information i.e. internal statistics,
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debug information, MAC and DMA registers etc.
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These can be read in several ways depending on the
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type of the information actually needed.
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For example a user can be use the ethtool support
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to get statistics: e.g. using: ethtool -S ethX
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(that shows the Management counters (MMC) if supported)
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or sees the MAC/DMA registers: e.g. using: ethtool -d ethX
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Compiling the Kernel with CONFIG_DEBUG_FS the driver will export the following
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debugfs entries:
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/sys/kernel/debug/stmmaceth/descriptors_status
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To show the DMA TX/RX descriptor rings
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Developer can also use the "debug" module parameter to get further debug
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information (please see: NETIF Msg Level).
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6) Energy Efficient Ethernet
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Energy Efficient Ethernet(EEE) enables IEEE 802.3 MAC sublayer along
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with a family of Physical layer to operate in the Low power Idle(LPI)
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mode. The EEE mode supports the IEEE 802.3 MAC operation at 100Mbps,
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1000Mbps & 10Gbps.
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The LPI mode allows power saving by switching off parts of the
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communication device functionality when there is no data to be
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transmitted & received. The system on both the side of the link can
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disable some functionalities & save power during the period of low-link
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utilization. The MAC controls whether the system should enter or exit
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the LPI mode & communicate this to PHY.
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As soon as the interface is opened, the driver verifies if the EEE can
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be supported. This is done by looking at both the DMA HW capability
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register and the PHY devices MCD registers.
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To enter in Tx LPI mode the driver needs to have a software timer
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that enable and disable the LPI mode when there is nothing to be
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transmitted.
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7) Precision Time Protocol (PTP)
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The driver supports the IEEE 1588-2002, Precision Time Protocol (PTP),
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which enables precise synchronization of clocks in measurement and
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control systems implemented with technologies such as network
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communication.
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In addition to the basic timestamp features mentioned in IEEE 1588-2002
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Timestamps, new GMAC cores support the advanced timestamp features.
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IEEE 1588-2008 that can be enabled when configure the Kernel.
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8) SGMII/RGMII supports
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New GMAC devices provide own way to manage RGMII/SGMII.
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This information is available at run-time by looking at the
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HW capability register. This means that the stmmac can manage
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auto-negotiation and link status w/o using the PHYLIB stuff
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In fact, the HW provides a subset of extended registers to
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restart the ANE, verify Full/Half duplex mode and Speed.
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Also thanks to these registers it is possible to look at the
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Auto-negotiated Link Parter Ability.
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