James Morse f2791551ce arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419 ... [ Upstream commit 05460849c3 ] Cores affected by Neoverse-N1 #1542419 could execute a stale instruction when a branch is updated to point to freshly generated instructions. To workaround this issue we need user-space to issue unnecessary icache maintenance that we can trap. Start by hiding CTR_EL0.DIC. Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Sasha Levin <sashal@kernel.org>		2020-04-29 16:32:56 +02:00
..
acpi_object_usage.rst	…
arm-acpi.rst	…
booting.rst	…
cpu-feature-registers.rst	…
elf_hwcaps.rst	…
hugetlbpage.rst	…
index.rst	…
kasan-offsets.sh	…
legacy_instructions.rst	…
memory.rst	…
perf.txt	…
pointer-authentication.rst	…
silicon-errata.rst	arm64: errata: Hide CTR_EL0.DIC on systems affected by Neoverse-N1 #1542419	2020-04-29 16:32:56 +02:00
sve.rst	…
tagged-address-abi.rst	…
tagged-pointers.rst	…