581 lines
19 KiB
C
581 lines
19 KiB
C
/* Copyright (C) 2003-2005 SBE, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/io.h>
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#include <linux/hdlc.h>
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#include "pmcc4_sysdep.h"
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#include "sbecom_inline_linux.h"
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#include "libsbew.h"
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#include "pmcc4.h"
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#include "comet.h"
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#include "comet_tables.h"
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extern int cxt1e1_log_level;
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#define COMET_NUM_SAMPLES 24 /* Number of entries in the waveform table */
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#define COMET_NUM_UNITS 5 /* Number of points per entry in table */
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/* forward references */
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static void SetPwrLevel(comet_t *comet);
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static void WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table);
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static void WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
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void *TWV_table[12] = {
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TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
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TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
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TWVShortHaul4, TWVShortHaul5,
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/** PORT POINT - 75 Ohm not supported **/
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TWV_E1_75Ohm,
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TWV_E1_120Ohm
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};
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static int
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lbo_tbl_lkup(int t1, int lbo) {
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/* error switches to default */
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if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
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if (t1)
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/* default T1 waveform table */
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lbo = CFG_LBO_LH0;
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else
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/* default E1 waveform table */
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lbo = CFG_LBO_E120;
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}
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/* make index ZERO relative */
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return lbo - 1;
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}
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void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
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u_int8_t moreParams)
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{
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u_int8_t isT1mode;
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/* T1 default */
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u_int8_t tix = CFG_LBO_LH0;
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isT1mode = IS_FRAME_ANY_T1(port_mode);
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/* T1 or E1 */
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if (isT1mode) {
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/* Select T1 Mode & PIO output enabled */
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pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
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/* default T1 waveform table */
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tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
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} else {
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/* Select E1 Mode & PIO output enabled */
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pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
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/* default E1 waveform table */
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tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
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}
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if (moreParams & CFG_LBO_MASK)
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/* dial-in requested waveform table */
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tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
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/* Tx line Intfc cfg Set for analog & no special patterns */
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/* Transmit Line Interface Config. */
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pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
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/* master test Ignore Test settings for now */
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/* making sure it's Default value */
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pci_write_32((u_int32_t *) &comet->mtest, 0x00);
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/* Turn on Center (CENT) and everything else off */
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/* RJAT cfg */
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pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
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/* Set Jitter Attenuation to recommend T1 values */
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if (isT1mode) {
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/* RJAT Divider N1 Control */
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pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
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/* RJAT Divider N2 Control */
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pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
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} else {
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/* RJAT Divider N1 Control */
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pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
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/* RJAT Divider N2 Control */
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pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
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}
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/* Turn on Center (CENT) and everything else off */
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/* TJAT Config. */
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pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
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/* Do not bypass jitter attenuation and bypass elastic store */
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/* rx opts */
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pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
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/* TJAT ctrl & TJAT divider ctrl */
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/* Set Jitter Attenuation to recommended T1 values */
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if (isT1mode) {
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/* TJAT Divider N1 Control */
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pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
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/* TJAT Divider N2 Control */
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pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
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} else {
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/* TJAT Divider N1 Control */
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pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
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/* TJAT Divider N2 Control */
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pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
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}
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/* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
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/* Select 193-bit frame format */
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if (isT1mode) {
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pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
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pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
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} else {
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/* Select 256-bit frame format */
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pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
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pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
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/* disable T1 data link receive */
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pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
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/* disable T1 data link transmit */
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pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
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}
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/* the following is a default value */
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/* Enable 8 out of 10 validation */
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/* t1RBOC enable(BOC:BitOriented Code) */
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pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
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if (isT1mode) {
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/* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
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/* 6 bit down, 5 bit up (assert) */
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pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
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/* line loopback activate pattern */
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pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
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/* deactivate code pattern (i.e.001) */
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pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
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}
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/* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
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/* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
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/* 60: t1 ALMI cfg */
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/* Configure Line Coding */
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switch (port_mode)
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{
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/* 1 - T1 B8ZS */
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case CFG_FRAME_SF:
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
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pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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/* 5:B8ZS */
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pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
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pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
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break;
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/* 2 - T1 B8ZS */
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case CFG_FRAME_ESF:
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
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/* Bit 5: T1 DataLink Enable */
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pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
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/* 5: T1 DataLink Enable */
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pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
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/* 4:ESF 5:ESFFA */
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pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
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/* 2:ESF */
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
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/* 4:ESF 5:B8ZS */
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pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
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/* 4:ESF */
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pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
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break;
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/* 3 - HDB3 */
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case CFG_FRAME_E1PLAIN:
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
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break;
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/* 4 - HDB3 */
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case CFG_FRAME_E1CAS:
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
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break;
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/* 5 - HDB3 */
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case CFG_FRAME_E1CRC:
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
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break;
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/* 6 - HDB3 */
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case CFG_FRAME_E1CRC_CAS:
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
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break;
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/* 7 - T1 AMI */
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case CFG_FRAME_SF_AMI:
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/* Enable AMI Line Decoding */
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
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pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
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pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
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pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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break;
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/* 8 - T1 AMI */
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case CFG_FRAME_ESF_AMI:
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/* Enable AMI Line Decoding */
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
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/* 5: T1 DataLink Enable */
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pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
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/* 5: T1 DataLink Enable */
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pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
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/* Bit 4:ESF 5:ESFFA */
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pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
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/* 2:ESF */
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
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/* 4:ESF */
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pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
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/* 4:ESF */
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pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
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break;
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/* 9 - AMI */
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case CFG_FRAME_E1PLAIN_AMI:
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/* Enable AMI Line Decoding */
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
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break;
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/* 10 - AMI */
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case CFG_FRAME_E1CAS_AMI:
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/* Enable AMI Line Decoding */
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
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break;
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/* 11 - AMI */
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case CFG_FRAME_E1CRC_AMI:
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/* Enable AMI Line Decoding */
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
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break;
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/* 12 - AMI */
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case CFG_FRAME_E1CRC_CAS_AMI:
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/* Enable AMI Line Decoding */
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pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
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pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
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pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
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pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
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break;
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} /* end switch */
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/***
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* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
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* CMODE=1: Clock slave mode with BRCLK as an input,
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* DE=0: Use falling edge of BRCLK for data,
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* FE=0: Use falling edge of BRCLK for frame,
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* CMS=0: Use backplane freq,
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* RATE[1:0]=0,0: T1
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***/
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/* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
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/* note "rate bits can only be set once after reset" */
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if (clockmaster)
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{
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/* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
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/* rate = 1.544 Mb/s */
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if (isT1mode)
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/* Comet 0 Master Mode(CMODE=0) */
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pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
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/* rate = 2.048 Mb/s */
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else
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/* Comet 0 Master Mode(CMODE=0) */
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pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
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/* 31: BRIF frame pulse cfg 06: tx timing options */
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/* Master Mode i.e.FPMODE=0 (@0x20) */
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pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
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if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
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{
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if (cxt1e1_log_level >= LOG_SBEBUG12)
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pr_info(">> %s: clockmaster internal clock\n", __func__);
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/* internal oscillator */
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pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
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} else {
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/* external clock source */
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if (cxt1e1_log_level >= LOG_SBEBUG12)
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pr_info(">> %s: clockmaster external clock\n", __func__);
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/* loop timing(external) */
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pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
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}
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} else {
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/* slave */
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if (isT1mode)
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/* Slave Mode(CMODE=1, see above) */
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pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
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else
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/* Slave Mode(CMODE=1)*/
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pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
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/* Slave Mode i.e. FPMODE=1 (@0x20) */
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pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
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if (cxt1e1_log_level >= LOG_SBEBUG12)
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pr_info(">> %s: clockslave internal clock\n", __func__);
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/* oscillator timing */
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pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
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}
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/* 32: BRIF parity F-bit cfg */
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/* Totem-pole operation */
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/* Receive Backplane Parity/F-bit */
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pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
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/* dc: RLPS equalizer V ref */
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/* Configuration */
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if (isT1mode)
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/* RLPS Equalizer Voltage */
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pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
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else
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/* RLPS Equalizer Voltage */
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pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
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/* Reserved bit set and SQUELCH enabled */
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/* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
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/* RLPS Configuration Status */
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pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
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if (isT1mode)
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/* ? */
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pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
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else
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/* ? */
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pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
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/* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
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/* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
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/* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
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/* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
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/*** Transmit side is always an Input, Slave Clock*/
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/* 40: BTIF cfg 41: loop timing(external) */
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/*BTIF frame pulse cfg */
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if (isT1mode)
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/* BTIF Configuration Reg. */
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pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
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else
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/* BTIF Configuration Reg. */
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pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
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/* BTIF Frame Pulse Config. */
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pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
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/* 0a: master diag 06: tx timing options */
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/* if set Comet to loop back */
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/* Comets set to normal */
|
|
pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
|
|
|
|
/* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */
|
|
/* Store is enabled. */
|
|
|
|
WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
|
|
if (isT1mode)
|
|
WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
|
|
else
|
|
WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
|
|
SetPwrLevel(comet);
|
|
}
|
|
|
|
/*
|
|
** Name: WrtXmtWaveform
|
|
** Description: Formulate the Data for the Pulse Waveform Storage
|
|
** Write register, (F2), from the sample and unit inputs.
|
|
** Write the data to the Pulse Waveform Storage Data register.
|
|
** Returns: Nothing
|
|
*/
|
|
static void
|
|
WrtXmtWaveform(ci_t *ci, comet_t *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
|
|
{
|
|
u_int8_t WaveformAddr;
|
|
|
|
WaveformAddr = (sample << 3) + (unit & 7);
|
|
pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
|
|
/* for write order preservation when Optimizing driver */
|
|
pci_flush_write(ci);
|
|
pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
|
|
}
|
|
|
|
/*
|
|
** Name: WrtXmtWaveformTbl
|
|
** Description: Fill in the Transmit Waveform Values
|
|
** for driving the transmitter DAC.
|
|
** Returns: Nothing
|
|
*/
|
|
static void
|
|
WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
|
|
u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
|
|
{
|
|
u_int32_t sample, unit;
|
|
|
|
for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
|
|
{
|
|
for (unit = 0; unit < COMET_NUM_UNITS; unit++)
|
|
WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
|
|
}
|
|
|
|
/* Enable transmitter and set output amplitude */
|
|
pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
|
|
}
|
|
|
|
|
|
/*
|
|
** Name: WrtXmtWaveform
|
|
** Description: Fill in the Receive Equalizer RAM from the desired
|
|
** table.
|
|
** Returns: Nothing
|
|
**
|
|
** Remarks: Per PM4351 Device Errata, Receive Equalizer RAM Initialization
|
|
** is coded with early setup of indirect address.
|
|
*/
|
|
|
|
static void
|
|
WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
|
|
{
|
|
u_int32_t ramaddr;
|
|
volatile u_int32_t value;
|
|
|
|
for (ramaddr = 0; ramaddr < 256; ramaddr++) {
|
|
/*** the following lines are per Errata 7, 2.5 ***/
|
|
{
|
|
/* Set up for a read operation */
|
|
pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
|
|
/* for write order preservation when Optimizing driver */
|
|
pci_flush_write(ci);
|
|
/* write the addr, initiate a read */
|
|
pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
|
|
/* for write order preservation when Optimizing driver */
|
|
pci_flush_write(ci);
|
|
/*
|
|
* wait 3 line rate clock cycles to ensure address bits are
|
|
* captured by T1/E1 clock
|
|
*/
|
|
|
|
/* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
|
|
OS_uwait(4, "wret");
|
|
}
|
|
|
|
value = *table++;
|
|
pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
|
|
pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
|
|
pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
|
|
pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
|
|
/* for write order preservation when Optimizing driver */
|
|
pci_flush_write(ci);
|
|
|
|
/* Storing RAM address, causes RAM to be updated */
|
|
|
|
/* Set up for a write operation */
|
|
pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
|
|
/* for write order preservation when optimizing driver */
|
|
pci_flush_write(ci);
|
|
/* write the addr, initiate a read */
|
|
pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
|
|
/* for write order preservation when optimizing driver */
|
|
pci_flush_write(ci);
|
|
|
|
/*
|
|
* wait 3 line rate clock cycles to ensure address bits are captured
|
|
* by T1/E1 clock
|
|
*/
|
|
/* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
|
|
OS_uwait(4, "wret");
|
|
}
|
|
|
|
/* Enable Equalizer & set it to use 256 periods */
|
|
pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
|
|
}
|
|
|
|
|
|
/*
|
|
** Name: SetPwrLevel
|
|
** Description: Implement power level setting algorithm described below
|
|
** Returns: Nothing
|
|
*/
|
|
|
|
static void
|
|
SetPwrLevel(comet_t *comet)
|
|
{
|
|
volatile u_int32_t temp;
|
|
|
|
/*
|
|
** Algorithm to Balance the Power Distribution of Ttip Tring
|
|
**
|
|
** Zero register F6
|
|
** Write 0x01 to register F4
|
|
** Write another 0x01 to register F4
|
|
** Read register F4
|
|
** Remove the 0x01 bit by Anding register F4 with 0xFE
|
|
** Write the resultant value to register F4
|
|
** Repeat these steps for register F5
|
|
** Write 0x01 to register F6
|
|
*/
|
|
/* XLPG Fuse Data Select */
|
|
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
|
|
/* XLPG Analog Test Positive control */
|
|
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
|
|
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
|
|
temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
|
|
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
|
|
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
|
|
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
|
|
/* XLPG Analog Test Negative control */
|
|
temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
|
|
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
|
|
/* XLPG */
|
|
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
|
|
}
|
|
|
|
|
|
/*
|
|
** Name: SetCometOps
|
|
** Description: Set up the selected Comet's clock edge drive for both
|
|
** the transmit out the analog side and receive to the
|
|
** backplane side.
|
|
** Returns: Nothing
|
|
*/
|
|
#if 0
|
|
static void
|
|
SetCometOps(comet_t *comet)
|
|
{
|
|
volatile u_int8_t rd_value;
|
|
|
|
if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
|
|
{
|
|
/* read the BRIF Configuration */
|
|
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
|
|
rd_value &= ~0x20;
|
|
pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
|
|
/* read the BRIF Frame Pulse Configuration */
|
|
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
|
|
rd_value &= ~0x20;
|
|
pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
|
|
} else {
|
|
/* read the BRIF Configuration */
|
|
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
|
|
rd_value |= 0x20;
|
|
pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
|
|
/* read the BRIF Frame Pulse Configuration */
|
|
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
|
|
rd_value |= 0x20;
|
|
pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/*** End-of-File ***/
|