5035b230e7
This is the second issue I noticed in reviewing the parisc TLB code. The fic instruction may use either the instruction or data TLB in flushing the instruction cache. Thus, on machines with a split TLB, we should also flush the data TLB after setting up the temporary alias registers. Although this has no functional impact, I changed the pdtlb and pitlb instructions to consistently use the index register %r0. These instructions do not support integer displacements. Tested on rp3440 and c8000. Signed-off-by: John David Anglin <dave.anglin@bell.net> Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by: Helge Deller <deller@gmx.de> |
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| .. | ||
| .gitignore | ||
| Makefile | ||
| asm-offsets.c | ||
| audit.c | ||
| binfmt_elf32.c | ||
| cache.c | ||
| compat_audit.c | ||
| drivers.c | ||
| entry.S | ||
| firmware.c | ||
| ftrace.c | ||
| hardware.c | ||
| head.S | ||
| hpmc.S | ||
| inventory.c | ||
| irq.c | ||
| module.c | ||
| pa7300lc.c | ||
| pacache.S | ||
| parisc_ksyms.c | ||
| pci-dma.c | ||
| pci.c | ||
| pdc_chassis.c | ||
| pdc_cons.c | ||
| perf.c | ||
| perf_asm.S | ||
| perf_images.h | ||
| process.c | ||
| processor.c | ||
| ptrace.c | ||
| real2.S | ||
| setup.c | ||
| signal.c | ||
| signal32.c | ||
| signal32.h | ||
| smp.c | ||
| stacktrace.c | ||
| sys_parisc.c | ||
| sys_parisc32.c | ||
| syscall.S | ||
| syscall_table.S | ||
| time.c | ||
| topology.c | ||
| traps.c | ||
| unaligned.c | ||
| unwind.c | ||
| vmlinux.lds.S | ||