64d2dc384e
The SWP instruction was deprecated in the ARMv6 architecture, superseded by the LDREX/STREX family of instructions for load-linked/store-conditional operations. The ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions are treated as undefined from reset, with the ability to enable them through the System Control Register SW bit. This patch adds the alternative solution to emulate the SWP and SWPB instructions using LDREX/STREX sequences, and log statistics to /proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when user RO. Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Kirill A. Shutemov <kirill@shutemov.name> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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.. | ||
.gitignore | ||
Makefile | ||
armksyms.c | ||
arthur.c | ||
asm-offsets.c | ||
atags.c | ||
atags.h | ||
bios32.c | ||
calls.S | ||
compat.c | ||
compat.h | ||
crash_dump.c | ||
crunch-bits.S | ||
crunch.c | ||
debug.S | ||
dma-isa.c | ||
dma.c | ||
early_printk.c | ||
ecard.c | ||
ecard.h | ||
elf.c | ||
entry-armv.S | ||
entry-common.S | ||
entry-header.S | ||
etm.c | ||
fiq.c | ||
ftrace.c | ||
head-common.S | ||
head-nommu.S | ||
head.S | ||
hw_breakpoint.c | ||
init_task.c | ||
io.c | ||
irq.c | ||
isa.c | ||
iwmmxt.S | ||
kgdb.c | ||
kprobes-decode.c | ||
kprobes.c | ||
leds.c | ||
machine_kexec.c | ||
module.c | ||
perf_event.c | ||
pmu.c | ||
process.c | ||
ptrace.c | ||
ptrace.h | ||
relocate_kernel.S | ||
return_address.c | ||
setup.c | ||
signal.c | ||
signal.h | ||
smp.c | ||
smp_scu.c | ||
smp_twd.c | ||
stacktrace.c | ||
swp_emulate.c | ||
sys_arm.c | ||
sys_oabi-compat.c | ||
tcm.c | ||
tcm.h | ||
thumbee.c | ||
time.c | ||
traps.c | ||
unwind.c | ||
vmlinux.lds.S | ||
xscale-cp0.c |