d0f349fbce
This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
159 lines
3.9 KiB
C
159 lines
3.9 KiB
C
/*
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* mxc_timer.h
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*
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* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
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*
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* Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*/
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#ifndef __PLAT_MXC_TIMER_H
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#define __PLAT_MXC_TIMER_H
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#include <linux/clk.h>
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#include <asm/hardware.h>
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#ifdef CONFIG_ARCH_IMX
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#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
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#define TIMER_INTERRUPT TIM1_INT
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#define TCTL_VAL TCTL_CLK_PCLK1
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#define TCTL_IRQEN (1<<4)
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#define TCTL_FRR (1<<8)
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#define TCTL_CLK_PCLK1 (1<<1)
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#define TCTL_CLK_PCLK1_4 (2<<1)
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#define TCTL_CLK_TIN (3<<1)
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#define TCTL_CLK_32 (4<<1)
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#define MXC_TCTL 0x00
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#define MXC_TPRER 0x04
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#define MXC_TCMP 0x08
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#define MXC_TCR 0x0c
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#define MXC_TCN 0x10
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#define MXC_TSTAT 0x14
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#define TSTAT_CAPT (1<<1)
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#define TSTAT_COMP (1<<0)
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static inline void gpt_irq_disable(void)
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{
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unsigned int tmp;
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tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
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__raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
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}
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static inline void gpt_irq_enable(void)
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{
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__raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
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TIMER_BASE + MXC_TCTL);
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}
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static void gpt_irq_acknowledge(void)
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{
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__raw_writel(0, TIMER_BASE + MXC_TSTAT);
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}
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#endif /* CONFIG_ARCH_IMX */
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#ifdef CONFIG_ARCH_MX2
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#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
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#define TIMER_INTERRUPT MXC_INT_GPT1
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#define MXC_TCTL 0x00
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#define TCTL_VAL TCTL_CLK_PCLK1
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#define TCTL_CLK_PCLK1 (1<<1)
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#define TCTL_CLK_PCLK1_4 (2<<1)
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#define TCTL_IRQEN (1<<4)
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#define TCTL_FRR (1<<8)
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#define MXC_TPRER 0x04
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#define MXC_TCMP 0x08
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#define MXC_TCR 0x0c
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#define MXC_TCN 0x10
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#define MXC_TSTAT 0x14
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#define TSTAT_CAPT (1<<1)
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#define TSTAT_COMP (1<<0)
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static inline void gpt_irq_disable(void)
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{
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unsigned int tmp;
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tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
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__raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
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}
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static inline void gpt_irq_enable(void)
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{
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__raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
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TIMER_BASE + MXC_TCTL);
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}
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static void gpt_irq_acknowledge(void)
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{
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__raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
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}
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#endif /* CONFIG_ARCH_MX2 */
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#ifdef CONFIG_ARCH_MX3
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#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
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#define TIMER_INTERRUPT MXC_INT_GPT
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#define MXC_TCTL 0x00
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#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
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#define TCTL_CLK_IPG (1<<6)
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#define TCTL_FRR (1<<9)
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#define TCTL_WAITEN (1<<3)
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#define MXC_TPRER 0x04
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#define MXC_TSTAT 0x08
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#define TSTAT_OF1 (1<<0)
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#define TSTAT_OF2 (1<<1)
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#define TSTAT_OF3 (1<<2)
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#define TSTAT_IF1 (1<<3)
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#define TSTAT_IF2 (1<<4)
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#define TSTAT_ROV (1<<5)
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#define MXC_IR 0x0c
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#define MXC_TCMP 0x10
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#define MXC_TCMP2 0x14
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#define MXC_TCMP3 0x18
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#define MXC_TCR 0x1c
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#define MXC_TCN 0x24
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static inline void gpt_irq_disable(void)
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{
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__raw_writel(0, TIMER_BASE + MXC_IR);
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}
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static inline void gpt_irq_enable(void)
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{
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__raw_writel(1<<0, TIMER_BASE + MXC_IR);
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}
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static inline void gpt_irq_acknowledge(void)
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{
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__raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
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}
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#endif /* CONFIG_ARCH_MX3 */
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#define TCTL_SWR (1<<15)
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#define TCTL_CC (1<<10)
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#define TCTL_OM (1<<9)
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#define TCTL_CAP_RIS (1<<6)
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#define TCTL_CAP_FAL (2<<6)
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#define TCTL_CAP_RIS_FAL (3<<6)
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#define TCTL_CAP_ENA (1<<5)
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#define TCTL_TEN (1<<0)
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#endif
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