443 lines
10 KiB
C
443 lines
10 KiB
C
#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/topology.h>
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#include <linux/cpu.h>
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#include <linux/range.h>
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#include <asm/amd_nb.h>
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#include <asm/pci_x86.h>
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#include <asm/pci-direct.h>
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#include "bus_numa.h"
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/*
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* This discovers the pcibus <-> node mapping on AMD K8.
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* also get peer root bus resource for io,mmio
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*/
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struct pci_hostbridge_probe {
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u32 bus;
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u32 slot;
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u32 vendor;
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u32 device;
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};
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static struct pci_hostbridge_probe pci_probes[] __initdata = {
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
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{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
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{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
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};
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static u64 __initdata fam10h_mmconf_start;
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static u64 __initdata fam10h_mmconf_end;
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static void __init get_pci_mmcfg_amd_fam10h_range(void)
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{
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u32 address;
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u64 base, msr;
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unsigned segn_busn_bits;
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/* assume all cpus from fam10h have mmconf */
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if (boot_cpu_data.x86 < 0x10)
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return;
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address = MSR_FAM10H_MMIO_CONF_BASE;
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rdmsrl(address, msr);
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/* mmconfig is not enable */
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if (!(msr & FAM10H_MMIO_CONF_ENABLE))
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return;
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base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
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segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
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FAM10H_MMIO_CONF_BUSRANGE_MASK;
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fam10h_mmconf_start = base;
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fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
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}
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#define RANGE_NUM 16
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/**
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* early_fill_mp_bus_to_node()
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* called before pcibios_scan_root and pci_scan_bus
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* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
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* Registers found in the K8 northbridge
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*/
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static int __init early_fill_mp_bus_info(void)
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{
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int i;
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int j;
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unsigned bus;
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unsigned slot;
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int node;
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int link;
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int def_node;
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int def_link;
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struct pci_root_info *info;
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u32 reg;
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struct resource *res;
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u64 start;
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u64 end;
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struct range range[RANGE_NUM];
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u64 val;
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u32 address;
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bool found;
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if (!early_pci_allowed())
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return -1;
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found = false;
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for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
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u32 id;
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u16 device;
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u16 vendor;
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bus = pci_probes[i].bus;
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slot = pci_probes[i].slot;
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id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
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vendor = id & 0xffff;
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device = (id>>16) & 0xffff;
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if (pci_probes[i].vendor == vendor &&
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pci_probes[i].device == device) {
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found = true;
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break;
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}
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}
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if (!found)
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return 0;
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pci_root_num = 0;
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for (i = 0; i < 4; i++) {
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int min_bus;
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int max_bus;
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reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
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/* Check if that register is enabled for bus range */
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if ((reg & 7) != 3)
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continue;
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min_bus = (reg >> 16) & 0xff;
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max_bus = (reg >> 24) & 0xff;
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node = (reg >> 4) & 0x07;
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#ifdef CONFIG_NUMA
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for (j = min_bus; j <= max_bus; j++)
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set_mp_bus_to_node(j, node);
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#endif
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link = (reg >> 8) & 0x03;
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info = &pci_root_info[pci_root_num];
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info->bus_min = min_bus;
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info->bus_max = max_bus;
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info->node = node;
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info->link = link;
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sprintf(info->name, "PCI Bus #%02x", min_bus);
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pci_root_num++;
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}
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/* get the default node and link for left over res */
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reg = read_pci_config(bus, slot, 0, 0x60);
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def_node = (reg >> 8) & 0x07;
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reg = read_pci_config(bus, slot, 0, 0x64);
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def_link = (reg >> 8) & 0x03;
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memset(range, 0, sizeof(range));
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add_range(range, RANGE_NUM, 0, 0, 0xffff + 1);
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/* io port resource */
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for (i = 0; i < 4; i++) {
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reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
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if (!(reg & 3))
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continue;
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start = reg & 0xfff000;
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reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
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node = reg & 0x07;
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link = (reg >> 4) & 0x03;
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end = (reg & 0xfff000) | 0xfff;
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/* find the position */
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == node && info->link == link)
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break;
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}
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if (j == pci_root_num)
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continue; /* not found */
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info = &pci_root_info[j];
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printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
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node, link, start, end);
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/* kernel only handle 16 bit only */
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if (end > 0xffff)
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end = 0xffff;
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update_res(info, start, end, IORESOURCE_IO, 1);
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subtract_range(range, RANGE_NUM, start, end + 1);
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}
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/* add left over io port range to def node/link, [0, 0xffff] */
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/* find the position */
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == def_node && info->link == def_link)
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break;
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}
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if (j < pci_root_num) {
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info = &pci_root_info[j];
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for (i = 0; i < RANGE_NUM; i++) {
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if (!range[i].end)
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continue;
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update_res(info, range[i].start, range[i].end - 1,
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IORESOURCE_IO, 1);
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}
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}
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memset(range, 0, sizeof(range));
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/* 0xfd00000000-0xffffffffff for HT */
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end = cap_resource((0xfdULL<<32) - 1);
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end++;
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add_range(range, RANGE_NUM, 0, 0, end);
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/* need to take out [0, TOM) for RAM*/
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address = MSR_K8_TOP_MEM1;
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rdmsrl(address, val);
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end = (val & 0xffffff800000ULL);
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printk(KERN_INFO "TOM: %016llx aka %lldM\n", end, end>>20);
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if (end < (1ULL<<32))
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subtract_range(range, RANGE_NUM, 0, end);
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/* get mmconfig */
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get_pci_mmcfg_amd_fam10h_range();
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/* need to take out mmconf range */
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if (fam10h_mmconf_end) {
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printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
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subtract_range(range, RANGE_NUM, fam10h_mmconf_start,
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fam10h_mmconf_end + 1);
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}
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/* mmio resource */
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for (i = 0; i < 8; i++) {
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reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
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if (!(reg & 3))
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continue;
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start = reg & 0xffffff00; /* 39:16 on 31:8*/
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start <<= 8;
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reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
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node = reg & 0x07;
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link = (reg >> 4) & 0x03;
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end = (reg & 0xffffff00);
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end <<= 8;
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end |= 0xffff;
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/* find the position */
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == node && info->link == link)
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break;
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}
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if (j == pci_root_num)
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continue; /* not found */
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info = &pci_root_info[j];
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printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
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node, link, start, end);
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/*
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* some sick allocation would have range overlap with fam10h
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* mmconf range, so need to update start and end.
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*/
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if (fam10h_mmconf_end) {
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int changed = 0;
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u64 endx = 0;
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if (start >= fam10h_mmconf_start &&
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start <= fam10h_mmconf_end) {
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start = fam10h_mmconf_end + 1;
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changed = 1;
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}
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if (end >= fam10h_mmconf_start &&
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end <= fam10h_mmconf_end) {
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end = fam10h_mmconf_start - 1;
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changed = 1;
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}
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if (start < fam10h_mmconf_start &&
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end > fam10h_mmconf_end) {
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/* we got a hole */
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endx = fam10h_mmconf_start - 1;
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update_res(info, start, endx, IORESOURCE_MEM, 0);
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subtract_range(range, RANGE_NUM, start,
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endx + 1);
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printk(KERN_CONT " ==> [%llx, %llx]", start, endx);
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start = fam10h_mmconf_end + 1;
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changed = 1;
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}
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if (changed) {
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if (start <= end) {
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printk(KERN_CONT " %s [%llx, %llx]", endx ? "and" : "==>", start, end);
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} else {
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printk(KERN_CONT "%s\n", endx?"":" ==> none");
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continue;
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}
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}
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}
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update_res(info, cap_resource(start), cap_resource(end),
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IORESOURCE_MEM, 1);
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subtract_range(range, RANGE_NUM, start, end + 1);
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printk(KERN_CONT "\n");
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}
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/* need to take out [4G, TOM2) for RAM*/
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/* SYS_CFG */
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address = MSR_K8_SYSCFG;
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rdmsrl(address, val);
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/* TOP_MEM2 is enabled? */
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if (val & (1<<21)) {
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/* TOP_MEM2 */
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address = MSR_K8_TOP_MEM2;
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rdmsrl(address, val);
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end = (val & 0xffffff800000ULL);
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printk(KERN_INFO "TOM2: %016llx aka %lldM\n", end, end>>20);
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subtract_range(range, RANGE_NUM, 1ULL<<32, end);
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}
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/*
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* add left over mmio range to def node/link ?
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* that is tricky, just record range in from start_min to 4G
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*/
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for (j = 0; j < pci_root_num; j++) {
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info = &pci_root_info[j];
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if (info->node == def_node && info->link == def_link)
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break;
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}
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if (j < pci_root_num) {
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info = &pci_root_info[j];
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for (i = 0; i < RANGE_NUM; i++) {
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if (!range[i].end)
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continue;
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update_res(info, cap_resource(range[i].start),
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cap_resource(range[i].end - 1),
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IORESOURCE_MEM, 1);
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}
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}
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for (i = 0; i < pci_root_num; i++) {
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int res_num;
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int busnum;
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info = &pci_root_info[i];
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res_num = info->res_num;
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busnum = info->bus_min;
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printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
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info->bus_min, info->bus_max, info->node, info->link);
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for (j = 0; j < res_num; j++) {
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res = &info->res[j];
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printk(KERN_DEBUG "bus: %02x index %x %pR\n",
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busnum, j, res);
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}
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}
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return 0;
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}
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#define ENABLE_CF8_EXT_CFG (1ULL << 46)
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static void __cpuinit enable_pci_io_ecs(void *unused)
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{
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u64 reg;
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rdmsrl(MSR_AMD64_NB_CFG, reg);
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if (!(reg & ENABLE_CF8_EXT_CFG)) {
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reg |= ENABLE_CF8_EXT_CFG;
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wrmsrl(MSR_AMD64_NB_CFG, reg);
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}
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}
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static int __cpuinit amd_cpu_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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int cpu = (long)hcpu;
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switch (action) {
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case CPU_ONLINE:
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case CPU_ONLINE_FROZEN:
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smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
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break;
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default:
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break;
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}
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return NOTIFY_OK;
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}
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static struct notifier_block __cpuinitdata amd_cpu_notifier = {
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.notifier_call = amd_cpu_notify,
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};
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static void __init pci_enable_pci_io_ecs(void)
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{
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#ifdef CONFIG_AMD_NB
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unsigned int i, n;
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for (n = i = 0; !n && amd_nb_bus_dev_ranges[i].dev_limit; ++i) {
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u8 bus = amd_nb_bus_dev_ranges[i].bus;
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u8 slot = amd_nb_bus_dev_ranges[i].dev_base;
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u8 limit = amd_nb_bus_dev_ranges[i].dev_limit;
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for (; slot < limit; ++slot) {
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u32 val = read_pci_config(bus, slot, 3, 0);
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if (!early_is_amd_nb(val))
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continue;
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val = read_pci_config(bus, slot, 3, 0x8c);
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if (!(val & (ENABLE_CF8_EXT_CFG >> 32))) {
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val |= ENABLE_CF8_EXT_CFG >> 32;
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write_pci_config(bus, slot, 3, 0x8c, val);
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}
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++n;
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}
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}
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pr_info("Extended Config Space enabled on %u nodes\n", n);
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#endif
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}
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static int __init pci_io_ecs_init(void)
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{
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int cpu;
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/* assume all cpus from fam10h have IO ECS */
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if (boot_cpu_data.x86 < 0x10)
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return 0;
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/* Try the PCI method first. */
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if (early_pci_allowed())
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pci_enable_pci_io_ecs();
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register_cpu_notifier(&amd_cpu_notifier);
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for_each_online_cpu(cpu)
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amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
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(void *)(long)cpu);
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pci_probe |= PCI_HAS_IO_ECS;
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return 0;
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}
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static int __init amd_postcore_init(void)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return 0;
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early_fill_mp_bus_info();
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pci_io_ecs_init();
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return 0;
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}
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postcore_initcall(amd_postcore_init);
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