7cee350816
This patch saves the value of the internal hash register at the end of an 'update' operation then restores this value before starting the next 'update'. This way the driver can now properly handle context switches. WARNING: only hardware versions from sama5d4x and later provide the needed interface to update the internal hash value. Especially, sama5d3x cannot implement this feature so context switches are still broken. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
#ifndef __ATMEL_SHA_REGS_H__
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#define __ATMEL_SHA_REGS_H__
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#define SHA_REG_DIGEST(x) (0x80 + ((x) * 0x04))
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#define SHA_REG_DIN(x) (0x40 + ((x) * 0x04))
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#define SHA_CR 0x00
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#define SHA_CR_START (1 << 0)
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#define SHA_CR_FIRST (1 << 4)
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#define SHA_CR_SWRST (1 << 8)
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#define SHA_CR_WUIHV (1 << 12)
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#define SHA_CR_WUIEHV (1 << 13)
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#define SHA_MR 0x04
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#define SHA_MR_MODE_MASK (0x3 << 0)
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#define SHA_MR_MODE_MANUAL 0x0
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#define SHA_MR_MODE_AUTO 0x1
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#define SHA_MR_MODE_PDC 0x2
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#define SHA_MR_PROCDLY (1 << 4)
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#define SHA_MR_UIHV (1 << 5)
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#define SHA_MR_UIEHV (1 << 6)
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#define SHA_MR_ALGO_SHA1 (0 << 8)
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#define SHA_MR_ALGO_SHA256 (1 << 8)
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#define SHA_MR_ALGO_SHA384 (2 << 8)
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#define SHA_MR_ALGO_SHA512 (3 << 8)
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#define SHA_MR_ALGO_SHA224 (4 << 8)
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#define SHA_MR_DUALBUFF (1 << 16)
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#define SHA_IER 0x10
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#define SHA_IDR 0x14
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#define SHA_IMR 0x18
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#define SHA_ISR 0x1C
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#define SHA_INT_DATARDY (1 << 0)
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#define SHA_INT_ENDTX (1 << 1)
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#define SHA_INT_TXBUFE (1 << 2)
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#define SHA_INT_URAD (1 << 8)
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#define SHA_ISR_URAT_MASK (0x7 << 12)
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#define SHA_ISR_URAT_IDR (0x0 << 12)
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#define SHA_ISR_URAT_ODR (0x1 << 12)
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#define SHA_ISR_URAT_MR (0x2 << 12)
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#define SHA_ISR_URAT_WO (0x5 << 12)
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#define SHA_HW_VERSION 0xFC
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#define SHA_TPR 0x108
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#define SHA_TCR 0x10C
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#define SHA_TNPR 0x118
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#define SHA_TNCR 0x11C
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#define SHA_PTCR 0x120
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#define SHA_PTCR_TXTEN (1 << 8)
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#define SHA_PTCR_TXTDIS (1 << 9)
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#define SHA_PTSR 0x124
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#define SHA_PTSR_TXTEN (1 << 8)
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#endif /* __ATMEL_SHA_REGS_H__ */
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