7dde0c0328
The codec reset pin is connected to several peripherals. When the reset is released, unfortunately the ADV7171 powers itself up rather than remaining in power-down mode. As we don't have a driver for this device, we end up needlessly consuming an additional 330mW. Not only that but we should have a way to arbitrate the reset signal. This patch provides that facility: we program the ADV7171 to sleep mode whenever the reset is released, and we release the reset when any one of the three peripherals requests the reset to be released. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
105 lines
4.3 KiB
C
105 lines
4.3 KiB
C
/*
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* arch/arm/mach-sa1100/include/mach/assabet.h
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*
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* Created 2000/06/05 by Nicolas Pitre <nico@fluxnic.net>
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*
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* This file contains the hardware specific definitions for Assabet
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* Only include this file from SA1100-specific files.
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*
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* 2000/05/23 John Dorsey <john+@cs.cmu.edu>
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* Definitions for Neponset added.
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*/
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#ifndef __ASM_ARCH_ASSABET_H
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#define __ASM_ARCH_ASSABET_H
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/* System Configuration Register flags */
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#define ASSABET_SCR_SDRAM_LOW (1<<2) /* SDRAM size (low bit) */
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#define ASSABET_SCR_SDRAM_HIGH (1<<3) /* SDRAM size (high bit) */
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#define ASSABET_SCR_FLASH_LOW (1<<4) /* Flash size (low bit) */
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#define ASSABET_SCR_FLASH_HIGH (1<<5) /* Flash size (high bit) */
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#define ASSABET_SCR_GFX (1<<8) /* Graphics Accelerator (0 = present) */
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#define ASSABET_SCR_SA1111 (1<<9) /* Neponset (0 = present) */
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#define ASSABET_SCR_INIT -1
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extern unsigned long SCR_value;
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#ifdef CONFIG_ASSABET_NEPONSET
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#define machine_has_neponset() ((SCR_value & ASSABET_SCR_SA1111) == 0)
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#else
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#define machine_has_neponset() (0)
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#endif
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/* Board Control Register */
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#define ASSABET_BCR_BASE 0xf1000000
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#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
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#define ASSABET_BCR_CF_PWR (1<<0) /* Compact Flash Power (1 = 3.3v, 0 = off) */
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#define ASSABET_BCR_CF_RST (1<<1) /* Compact Flash Reset (1 = power up reset) */
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#define ASSABET_BCR_NGFX_RST (1<<1) /* Graphics Accelerator Reset (0 = hold reset) */
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#define ASSABET_BCR_NCODEC_RST (1<<2) /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
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#define ASSABET_BCR_IRDA_FSEL (1<<3) /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
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#define ASSABET_BCR_IRDA_MD0 (1<<4) /* Range/Power select */
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#define ASSABET_BCR_IRDA_MD1 (1<<5) /* Range/Power select */
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#define ASSABET_BCR_STEREO_LB (1<<6) /* Stereo Loopback */
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#define ASSABET_BCR_CF_BUS_OFF (1<<7) /* Compact Flash bus (0 = on, 1 = off (float)) */
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#define ASSABET_BCR_AUDIO_ON (1<<8) /* Audio power on */
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#define ASSABET_BCR_LIGHT_ON (1<<9) /* Backlight */
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#define ASSABET_BCR_LCD_12RGB (1<<10) /* 0 = 16RGB, 1 = 12RGB */
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#define ASSABET_BCR_LCD_ON (1<<11) /* LCD power on */
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#define ASSABET_BCR_RS232EN (1<<12) /* RS232 transceiver enable */
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#define ASSABET_BCR_LED_RED (1<<13) /* D9 (0 = on, 1 = off) */
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#define ASSABET_BCR_LED_GREEN (1<<14) /* D8 (0 = on, 1 = off) */
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#define ASSABET_BCR_VIB_ON (1<<15) /* Vibration motor (quiet alert) */
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#define ASSABET_BCR_COM_DTR (1<<16) /* COMport Data Terminal Ready */
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#define ASSABET_BCR_COM_RTS (1<<17) /* COMport Request To Send */
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#define ASSABET_BCR_RAD_WU (1<<18) /* Radio wake up interrupt */
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#define ASSABET_BCR_SMB_EN (1<<19) /* System management bus enable */
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#define ASSABET_BCR_TV_IR_DEC (1<<20) /* TV IR Decode Enable (not implemented) */
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#define ASSABET_BCR_QMUTE (1<<21) /* Quick Mute */
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#define ASSABET_BCR_RAD_ON (1<<22) /* Radio Power On */
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#define ASSABET_BCR_SPK_OFF (1<<23) /* 1 = Speaker amplifier power off */
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#ifdef CONFIG_SA1100_ASSABET
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extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
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#else
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#define ASSABET_BCR_frob(x,y) do { } while (0)
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#endif
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extern void assabet_uda1341_reset(int set);
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#define ASSABET_BCR_set(x) ASSABET_BCR_frob((x), (x))
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#define ASSABET_BCR_clear(x) ASSABET_BCR_frob((x), 0)
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#define ASSABET_BSR_BASE 0xf1000000
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#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
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#define ASSABET_BSR_RS232_VALID (1 << 24)
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#define ASSABET_BSR_COM_DCD (1 << 25)
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#define ASSABET_BSR_COM_CTS (1 << 26)
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#define ASSABET_BSR_COM_DSR (1 << 27)
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#define ASSABET_BSR_RAD_CTS (1 << 28)
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#define ASSABET_BSR_RAD_DSR (1 << 29)
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#define ASSABET_BSR_RAD_DCD (1 << 30)
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#define ASSABET_BSR_RAD_RI (1 << 31)
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/* GPIOs (bitmasks) for which the generic definition doesn't say much */
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#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
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#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
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#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
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#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
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#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
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#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
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/* These are gpiolib GPIO numbers, not bitmasks */
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#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */
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#define ASSABET_GPIO_CF_CD 22 /* CF CD */
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#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */
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#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */
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#endif
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