ccc0772927
The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared before a new value can be or-ed in. Signed-off-by: Thomas Breitung <thomas.breitung@izt-labs.de> Signed-off-by: Wolfgang Ocker <weo@reccoware.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
243 lines
7.3 KiB
C
243 lines
7.3 KiB
C
/*
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* Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author:
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* Zhang Wei <wei.zhang@freescale.com>, Jul 2007
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* Ebony Zhu <ebony.zhu@freescale.com>, May 2007
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#ifndef __DMA_FSLDMA_H
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#define __DMA_FSLDMA_H
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#include <linux/device.h>
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#include <linux/dmapool.h>
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#include <linux/dmaengine.h>
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/* Define data structures needed by Freescale
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* MPC8540 and MPC8349 DMA controller.
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*/
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#define FSL_DMA_MR_CS 0x00000001
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#define FSL_DMA_MR_CC 0x00000002
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#define FSL_DMA_MR_CA 0x00000008
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#define FSL_DMA_MR_EIE 0x00000040
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#define FSL_DMA_MR_XFE 0x00000020
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#define FSL_DMA_MR_EOLNIE 0x00000100
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#define FSL_DMA_MR_EOLSIE 0x00000080
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#define FSL_DMA_MR_EOSIE 0x00000200
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#define FSL_DMA_MR_CDSM 0x00000010
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#define FSL_DMA_MR_CTM 0x00000004
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#define FSL_DMA_MR_EMP_EN 0x00200000
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#define FSL_DMA_MR_EMS_EN 0x00040000
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#define FSL_DMA_MR_DAHE 0x00002000
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#define FSL_DMA_MR_SAHE 0x00001000
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#define FSL_DMA_MR_SAHTS_MASK 0x0000C000
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#define FSL_DMA_MR_DAHTS_MASK 0x00030000
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#define FSL_DMA_MR_BWC_MASK 0x0f000000
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/*
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* Bandwidth/pause control determines how many bytes a given
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* channel is allowed to transfer before the DMA engine pauses
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* the current channel and switches to the next channel
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*/
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#define FSL_DMA_MR_BWC 0x0A000000
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/* Special MR definition for MPC8349 */
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#define FSL_DMA_MR_EOTIE 0x00000080
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#define FSL_DMA_MR_PRC_RM 0x00000800
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#define FSL_DMA_SR_CH 0x00000020
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#define FSL_DMA_SR_PE 0x00000010
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#define FSL_DMA_SR_CB 0x00000004
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#define FSL_DMA_SR_TE 0x00000080
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#define FSL_DMA_SR_EOSI 0x00000002
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#define FSL_DMA_SR_EOLSI 0x00000001
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#define FSL_DMA_SR_EOCDI 0x00000001
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#define FSL_DMA_SR_EOLNI 0x00000008
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#define FSL_DMA_SATR_SBPATMU 0x20000000
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#define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000
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#define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000
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#define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000
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#define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000
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#define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000
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#define FSL_DMA_DATR_DBPATMU 0x20000000
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#define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000
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#define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000
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#define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000
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#define FSL_DMA_EOL ((u64)0x1)
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#define FSL_DMA_SNEN ((u64)0x10)
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#define FSL_DMA_EOSIE 0x8
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#define FSL_DMA_NLDA_MASK (~(u64)0x1f)
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#define FSL_DMA_BCR_MAX_CNT 0x03ffffffu
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#define FSL_DMA_DGSR_TE 0x80
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#define FSL_DMA_DGSR_CH 0x20
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#define FSL_DMA_DGSR_PE 0x10
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#define FSL_DMA_DGSR_EOLNI 0x08
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#define FSL_DMA_DGSR_CB 0x04
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#define FSL_DMA_DGSR_EOSI 0x02
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#define FSL_DMA_DGSR_EOLSI 0x01
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#define FSL_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
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BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
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BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
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typedef u64 __bitwise v64;
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typedef u32 __bitwise v32;
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struct fsl_dma_ld_hw {
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v64 src_addr;
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v64 dst_addr;
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v64 next_ln_addr;
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v32 count;
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v32 reserve;
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} __attribute__((aligned(32)));
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struct fsl_desc_sw {
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struct fsl_dma_ld_hw hw;
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struct list_head node;
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struct list_head tx_list;
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struct dma_async_tx_descriptor async_tx;
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} __attribute__((aligned(32)));
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struct fsldma_chan_regs {
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u32 mr; /* 0x00 - Mode Register */
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u32 sr; /* 0x04 - Status Register */
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u64 cdar; /* 0x08 - Current descriptor address register */
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u64 sar; /* 0x10 - Source Address Register */
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u64 dar; /* 0x18 - Destination Address Register */
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u32 bcr; /* 0x20 - Byte Count Register */
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u64 ndar; /* 0x24 - Next Descriptor Address Register */
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};
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struct fsldma_chan;
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#define FSL_DMA_MAX_CHANS_PER_DEVICE 8
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struct fsldma_device {
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void __iomem *regs; /* DGSR register base */
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struct device *dev;
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struct dma_device common;
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struct fsldma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE];
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u32 feature; /* The same as DMA channels */
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int irq; /* Channel IRQ */
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};
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/* Define macros for fsldma_chan->feature property */
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#define FSL_DMA_LITTLE_ENDIAN 0x00000000
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#define FSL_DMA_BIG_ENDIAN 0x00000001
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#define FSL_DMA_IP_MASK 0x00000ff0
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#define FSL_DMA_IP_85XX 0x00000010
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#define FSL_DMA_IP_83XX 0x00000020
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#define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
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#define FSL_DMA_CHAN_START_EXT 0x00002000
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#ifdef CONFIG_PM
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struct fsldma_chan_regs_save {
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u32 mr;
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};
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enum fsldma_pm_state {
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RUNNING = 0,
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SUSPENDED,
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};
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#endif
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struct fsldma_chan {
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char name[8]; /* Channel name */
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struct fsldma_chan_regs __iomem *regs;
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spinlock_t desc_lock; /* Descriptor operation lock */
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/*
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* Descriptors which are queued to run, but have not yet been
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* submitted to the hardware for execution
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*/
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struct list_head ld_pending;
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/*
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* Descriptors which are currently being executed by the hardware
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*/
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struct list_head ld_running;
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/*
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* Descriptors which have finished execution by the hardware. These
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* descriptors have already had their cleanup actions run. They are
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* waiting for the ACK bit to be set by the async_tx API.
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*/
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struct list_head ld_completed; /* Link descriptors queue */
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struct dma_chan common; /* DMA common channel */
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struct dma_pool *desc_pool; /* Descriptors pool */
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struct device *dev; /* Channel device */
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int irq; /* Channel IRQ */
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int id; /* Raw id of this channel */
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struct tasklet_struct tasklet;
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u32 feature;
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bool idle; /* DMA controller is idle */
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#ifdef CONFIG_PM
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struct fsldma_chan_regs_save regs_save;
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enum fsldma_pm_state pm_state;
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#endif
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void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
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void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
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void (*set_src_loop_size)(struct fsldma_chan *fsl_chan, int size);
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void (*set_dst_loop_size)(struct fsldma_chan *fsl_chan, int size);
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void (*set_request_count)(struct fsldma_chan *fsl_chan, int size);
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};
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#define to_fsl_chan(chan) container_of(chan, struct fsldma_chan, common)
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#define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node)
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#define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx)
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#ifndef __powerpc64__
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static u64 in_be64(const u64 __iomem *addr)
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{
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return ((u64)in_be32((u32 __iomem *)addr) << 32) |
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(in_be32((u32 __iomem *)addr + 1));
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}
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static void out_be64(u64 __iomem *addr, u64 val)
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{
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out_be32((u32 __iomem *)addr, val >> 32);
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out_be32((u32 __iomem *)addr + 1, (u32)val);
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}
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/* There is no asm instructions for 64 bits reverse loads and stores */
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static u64 in_le64(const u64 __iomem *addr)
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{
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return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) |
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(in_le32((u32 __iomem *)addr));
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}
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static void out_le64(u64 __iomem *addr, u64 val)
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{
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out_le32((u32 __iomem *)addr + 1, val >> 32);
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out_le32((u32 __iomem *)addr, (u32)val);
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}
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#endif
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#define DMA_IN(fsl_chan, addr, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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in_be##width(addr) : in_le##width(addr))
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#define DMA_OUT(fsl_chan, addr, val, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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out_be##width(addr, val) : out_le##width(addr, val))
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#define DMA_TO_CPU(fsl_chan, d, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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be##width##_to_cpu((__force __be##width)(v##width)d) : \
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le##width##_to_cpu((__force __le##width)(v##width)d))
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#define CPU_TO_DMA(fsl_chan, c, width) \
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(((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \
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(__force v##width)cpu_to_be##width(c) : \
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(__force v##width)cpu_to_le##width(c))
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#endif /* __DMA_FSLDMA_H */
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