248b122b13
All our revision macros are defined with the entire 32-bits which we read from GSNPSID register, so we must cache all 32-bits properly rather than masking the top 16-bits. This will fix all revision checks we have on current driver. Signed-off-by: Felipe Balbi <balbi@ti.com>
485 lines
12 KiB
C
485 lines
12 KiB
C
/**
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* core.c - DesignWare USB3 DRD Controller Core file
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/list.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/module.h>
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#include "core.h"
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#include "gadget.h"
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#include "io.h"
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#include "debug.h"
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/**
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* dwc3_core_soft_reset - Issues core soft reset and PHY reset
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* @dwc: pointer to our context structure
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*/
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static void dwc3_core_soft_reset(struct dwc3 *dwc)
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{
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u32 reg;
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/* Before Resetting PHY, put Core in Reset */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg |= DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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/* Assert USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/* Assert USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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mdelay(100);
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/* Clear USB3 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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/* Clear USB2 PHY reset */
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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/* After PHYs are stable we can take Core out of reset state */
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reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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reg &= ~DWC3_GCTL_CORESOFTRESET;
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dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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}
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/**
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* dwc3_free_one_event_buffer - Frees one event buffer
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* @dwc: Pointer to our controller context structure
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* @evt: Pointer to event buffer to be freed
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*/
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static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
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struct dwc3_event_buffer *evt)
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{
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dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
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kfree(evt);
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}
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/**
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* dwc3_alloc_one_event_buffer - Allocated one event buffer structure
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* @dwc: Pointer to our controller context structure
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* @length: size of the event buffer
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*
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* Returns a pointer to the allocated event buffer structure on succes
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* otherwise ERR_PTR(errno).
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*/
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static struct dwc3_event_buffer *__devinit
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dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
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{
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struct dwc3_event_buffer *evt;
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evt = kzalloc(sizeof(*evt), GFP_KERNEL);
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if (!evt)
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return ERR_PTR(-ENOMEM);
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evt->dwc = dwc;
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evt->length = length;
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evt->buf = dma_alloc_coherent(dwc->dev, length,
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&evt->dma, GFP_KERNEL);
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if (!evt->buf) {
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kfree(evt);
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return ERR_PTR(-ENOMEM);
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}
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return evt;
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}
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/**
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* dwc3_free_event_buffers - frees all allocated event buffers
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* @dwc: Pointer to our controller context structure
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*/
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static void dwc3_free_event_buffers(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int i;
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for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
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evt = dwc->ev_buffs[i];
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if (evt) {
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dwc3_free_one_event_buffer(dwc, evt);
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dwc->ev_buffs[i] = NULL;
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}
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}
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}
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/**
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* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
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* @dwc: Pointer to out controller context structure
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* @num: number of event buffers to allocate
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* @length: size of event buffer
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*
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* Returns 0 on success otherwise negative errno. In error the case, dwc
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* may contain some buffers allocated but not all which were requested.
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*/
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static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned num,
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unsigned length)
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{
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int i;
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for (i = 0; i < num; i++) {
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struct dwc3_event_buffer *evt;
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evt = dwc3_alloc_one_event_buffer(dwc, length);
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if (IS_ERR(evt)) {
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dev_err(dwc->dev, "can't allocate event buffer\n");
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return PTR_ERR(evt);
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}
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dwc->ev_buffs[i] = evt;
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}
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return 0;
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}
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/**
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* dwc3_event_buffers_setup - setup our allocated event buffers
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* @dwc: Pointer to out controller context structure
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*
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* Returns 0 on success otherwise negative errno.
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*/
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static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int n;
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for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
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evt = dwc->ev_buffs[n];
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dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
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evt->buf, (unsigned long long) evt->dma,
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evt->length);
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
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lower_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
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upper_32_bits(evt->dma));
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
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evt->length & 0xffff);
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
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}
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return 0;
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}
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static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
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{
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struct dwc3_event_buffer *evt;
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int n;
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for (n = 0; n < DWC3_EVENT_BUFFERS_NUM; n++) {
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evt = dwc->ev_buffs[n];
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dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
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dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
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}
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}
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static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
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{
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struct dwc3_hwparams *parms = &dwc->hwparams;
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parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
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parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
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parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
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parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
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parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
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parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
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parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
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parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
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parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
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}
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/**
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* dwc3_core_init - Low-level initialization of DWC3 Core
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* @dwc: Pointer to our controller context structure
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*
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* Returns 0 on success otherwise negative errno.
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*/
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static int __devinit dwc3_core_init(struct dwc3 *dwc)
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{
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unsigned long timeout;
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u32 reg;
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int ret;
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reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
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/* This should read as U3 followed by revision number */
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if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
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dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
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ret = -ENODEV;
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goto err0;
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}
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dwc->revision = reg;
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dwc3_core_soft_reset(dwc);
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/* issue device SoftReset too */
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timeout = jiffies + msecs_to_jiffies(500);
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dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
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do {
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reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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if (!(reg & DWC3_DCTL_CSFTRST))
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break;
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if (time_after(jiffies, timeout)) {
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dev_err(dwc->dev, "Reset Timed Out\n");
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ret = -ETIMEDOUT;
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goto err0;
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}
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cpu_relax();
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} while (true);
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ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_NUM,
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DWC3_EVENT_BUFFERS_SIZE);
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if (ret) {
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dev_err(dwc->dev, "failed to allocate event buffers\n");
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ret = -ENOMEM;
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goto err1;
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}
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ret = dwc3_event_buffers_setup(dwc);
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if (ret) {
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dev_err(dwc->dev, "failed to setup event buffers\n");
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goto err1;
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}
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dwc3_cache_hwparams(dwc);
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return 0;
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err1:
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dwc3_free_event_buffers(dwc);
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err0:
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return ret;
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}
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static void dwc3_core_exit(struct dwc3 *dwc)
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{
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dwc3_event_buffers_cleanup(dwc);
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dwc3_free_event_buffers(dwc);
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}
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#define DWC3_ALIGN_MASK (16 - 1)
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static int __devinit dwc3_probe(struct platform_device *pdev)
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{
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const struct platform_device_id *id = platform_get_device_id(pdev);
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struct resource *res;
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struct dwc3 *dwc;
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void __iomem *regs;
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unsigned int features = id->driver_data;
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int ret = -ENOMEM;
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int irq;
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void *mem;
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mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
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if (!mem) {
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dev_err(&pdev->dev, "not enough memory\n");
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goto err0;
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}
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dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
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dwc->mem = mem;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "missing resource\n");
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goto err1;
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}
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res = request_mem_region(res->start, resource_size(res),
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dev_name(&pdev->dev));
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if (!res) {
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dev_err(&pdev->dev, "can't request mem region\n");
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goto err1;
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}
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regs = ioremap(res->start, resource_size(res));
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if (!regs) {
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dev_err(&pdev->dev, "ioremap failed\n");
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goto err2;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "missing IRQ\n");
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goto err3;
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}
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spin_lock_init(&dwc->lock);
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platform_set_drvdata(pdev, dwc);
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dwc->regs = regs;
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dwc->regs_size = resource_size(res);
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dwc->dev = &pdev->dev;
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dwc->irq = irq;
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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pm_runtime_forbid(&pdev->dev);
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ret = dwc3_core_init(dwc);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialize core\n");
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goto err3;
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}
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if (features & DWC3_HAS_PERIPHERAL) {
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ret = dwc3_gadget_init(dwc);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialized gadget\n");
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goto err4;
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}
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}
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ret = dwc3_debugfs_init(dwc);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialize debugfs\n");
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goto err5;
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}
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pm_runtime_allow(&pdev->dev);
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return 0;
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err5:
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if (features & DWC3_HAS_PERIPHERAL)
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dwc3_gadget_exit(dwc);
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err4:
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dwc3_core_exit(dwc);
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err3:
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iounmap(regs);
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err2:
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release_mem_region(res->start, resource_size(res));
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err1:
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kfree(dwc->mem);
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err0:
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return ret;
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}
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static int __devexit dwc3_remove(struct platform_device *pdev)
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{
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const struct platform_device_id *id = platform_get_device_id(pdev);
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struct dwc3 *dwc = platform_get_drvdata(pdev);
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struct resource *res;
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unsigned int features = id->driver_data;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pm_runtime_put(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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dwc3_debugfs_exit(dwc);
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if (features & DWC3_HAS_PERIPHERAL)
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dwc3_gadget_exit(dwc);
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dwc3_core_exit(dwc);
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release_mem_region(res->start, resource_size(res));
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iounmap(dwc->regs);
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kfree(dwc->mem);
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return 0;
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}
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static const struct platform_device_id dwc3_id_table[] __devinitconst = {
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{
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.name = "dwc3-omap",
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.driver_data = (DWC3_HAS_PERIPHERAL
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| DWC3_HAS_XHCI
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| DWC3_HAS_OTG),
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},
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{
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.name = "dwc3-pci",
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.driver_data = DWC3_HAS_PERIPHERAL,
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},
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{ }, /* Terminating Entry */
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};
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MODULE_DEVICE_TABLE(platform, dwc3_id_table);
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static struct platform_driver dwc3_driver = {
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.probe = dwc3_probe,
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.remove = __devexit_p(dwc3_remove),
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.driver = {
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.name = "dwc3",
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},
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.id_table = dwc3_id_table,
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};
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MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
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MODULE_LICENSE("Dual BSD/GPL");
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MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
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static int __devinit dwc3_init(void)
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{
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return platform_driver_register(&dwc3_driver);
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}
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module_init(dwc3_init);
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static void __exit dwc3_exit(void)
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{
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platform_driver_unregister(&dwc3_driver);
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}
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module_exit(dwc3_exit);
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