223 lines
5.3 KiB
C
223 lines
5.3 KiB
C
#ifndef __ASM_ARM_CPUTYPE_H
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#define __ASM_ARM_CPUTYPE_H
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#include <linux/stringify.h>
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#include <linux/kernel.h>
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#define CPUID_ID 0
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#define CPUID_CACHETYPE 1
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#define CPUID_TCM 2
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#define CPUID_TLBTYPE 3
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#define CPUID_MPUIR 4
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#define CPUID_MPIDR 5
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#ifdef CONFIG_CPU_V7M
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#define CPUID_EXT_PFR0 0x40
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#define CPUID_EXT_PFR1 0x44
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#define CPUID_EXT_DFR0 0x48
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#define CPUID_EXT_AFR0 0x4c
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#define CPUID_EXT_MMFR0 0x50
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#define CPUID_EXT_MMFR1 0x54
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#define CPUID_EXT_MMFR2 0x58
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#define CPUID_EXT_MMFR3 0x5c
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#define CPUID_EXT_ISAR0 0x60
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#define CPUID_EXT_ISAR1 0x64
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#define CPUID_EXT_ISAR2 0x68
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#define CPUID_EXT_ISAR3 0x6c
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#define CPUID_EXT_ISAR4 0x70
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#define CPUID_EXT_ISAR5 0x74
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#else
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#define CPUID_EXT_PFR0 "c1, 0"
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#define CPUID_EXT_PFR1 "c1, 1"
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#define CPUID_EXT_DFR0 "c1, 2"
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#define CPUID_EXT_AFR0 "c1, 3"
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#define CPUID_EXT_MMFR0 "c1, 4"
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#define CPUID_EXT_MMFR1 "c1, 5"
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#define CPUID_EXT_MMFR2 "c1, 6"
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#define CPUID_EXT_MMFR3 "c1, 7"
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#define CPUID_EXT_ISAR0 "c2, 0"
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#define CPUID_EXT_ISAR1 "c2, 1"
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#define CPUID_EXT_ISAR2 "c2, 2"
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#define CPUID_EXT_ISAR3 "c2, 3"
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#define CPUID_EXT_ISAR4 "c2, 4"
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#define CPUID_EXT_ISAR5 "c2, 5"
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#endif
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#define MPIDR_SMP_BITMASK (0x3 << 30)
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#define MPIDR_SMP_VALUE (0x2 << 30)
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#define MPIDR_MT_BITMASK (0x1 << 24)
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#define MPIDR_HWID_BITMASK 0xFFFFFF
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#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
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#define MPIDR_LEVEL_BITS 8
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
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((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
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#define ARM_CPU_IMP_ARM 0x41
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#define ARM_CPU_IMP_INTEL 0x69
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#define ARM_CPU_PART_ARM1136 0xB360
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#define ARM_CPU_PART_ARM1156 0xB560
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#define ARM_CPU_PART_ARM1176 0xB760
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#define ARM_CPU_PART_ARM11MPCORE 0xB020
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#define ARM_CPU_PART_CORTEX_A8 0xC080
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#define ARM_CPU_PART_CORTEX_A9 0xC090
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#define ARM_CPU_PART_CORTEX_A5 0xC050
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#define ARM_CPU_PART_CORTEX_A15 0xC0F0
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#define ARM_CPU_PART_CORTEX_A7 0xC070
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#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
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#define ARM_CPU_XSCALE_ARCH_V1 0x2000
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#define ARM_CPU_XSCALE_ARCH_V2 0x4000
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#define ARM_CPU_XSCALE_ARCH_V3 0x6000
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extern unsigned int processor_id;
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#ifdef CONFIG_CPU_CP15
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#define read_cpuid(reg) \
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({ \
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unsigned int __val; \
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asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
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: "=r" (__val) \
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: \
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: "cc"); \
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__val; \
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})
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/*
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* The memory clobber prevents gcc 4.5 from reordering the mrc before
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* any is_smp() tests, which can cause undefined instruction aborts on
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* ARM1136 r0 due to the missing extended CP15 registers.
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*/
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#define read_cpuid_ext(ext_reg) \
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({ \
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unsigned int __val; \
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asm("mrc p15, 0, %0, c0, " ext_reg \
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: "=r" (__val) \
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: \
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: "memory"); \
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__val; \
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})
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#elif defined(CONFIG_CPU_V7M)
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#include <asm/io.h>
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#include <asm/v7m.h>
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#define read_cpuid(reg) \
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({ \
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WARN_ON_ONCE(1); \
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0; \
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})
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static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
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{
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return readl(BASEADDR_V7M_SCB + offset);
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}
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#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
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/*
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* read_cpuid and read_cpuid_ext should only ever be called on machines that
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* have cp15 so warn on other usages.
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*/
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#define read_cpuid(reg) \
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({ \
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WARN_ON_ONCE(1); \
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0; \
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})
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#define read_cpuid_ext(reg) read_cpuid(reg)
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#endif /* ifdef CONFIG_CPU_CP15 / else */
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#ifdef CONFIG_CPU_CP15
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* rather than directly reading processor_id or read_cpuid() directly.
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*/
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return read_cpuid(CPUID_ID);
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}
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#elif defined(CONFIG_CPU_V7M)
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
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}
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#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return processor_id;
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}
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#endif /* ifdef CONFIG_CPU_CP15 / else */
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static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
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{
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return (read_cpuid_id() & 0xFF000000) >> 24;
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}
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static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
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{
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return read_cpuid_id() & 0xFFF0;
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}
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static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
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{
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return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
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}
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static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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{
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return read_cpuid(CPUID_CACHETYPE);
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}
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static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
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{
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return read_cpuid(CPUID_TCM);
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}
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static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
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{
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return read_cpuid(CPUID_MPIDR);
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}
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/*
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* Intel's XScale3 core supports some v6 features (supersections, L2)
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* but advertises itself as v5 as it does not support the v6 ISA. For
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* this reason, we need a way to explicitly test for this type of CPU.
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*/
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#ifndef CONFIG_CPU_XSC3
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#define cpu_is_xsc3() 0
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#else
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static inline int cpu_is_xsc3(void)
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{
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unsigned int id;
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id = read_cpuid_id() & 0xffffe000;
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/* It covers both Intel ID and Marvell ID */
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if ((id == 0x69056000) || (id == 0x56056000))
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return 1;
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return 0;
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}
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#endif
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#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
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#define cpu_is_xscale() 0
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#else
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#define cpu_is_xscale() 1
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#endif
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#endif
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