linux/arch/mips/lib
Maciej W. Rozycki 3bcb03f3a7 MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'
Move the initialisation of the CP0.Wired register implemented by Toshiba
TX3922 and TX3927 processors from `tx39_cache_init' to `tlb_init' where
it belongs, correcting code structure and making sure initialisation
does not rely on `tx39_cache_init' being called before `tlb_init' to
work correctly.

Make `r3k_have_wired_reg' static as it's no longer externally referred
to; remove a stale declaration too.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10195/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-21 21:52:41 +02:00
..
ashldi3.c
ashrdi3.c
bitops.c
cmpdi2.c
csum_partial.S
delay.c
dump_tlb.c
iomap-pci.c
iomap.c
libgcc.h
lshrdi3.c
Makefile
memcpy.S
memset.S
mips-atomic.c
r3k_dump_tlb.c
strlen_user.S
strncpy_user.S
strnlen_user.S
ucmpdi2.c
uncached.c