2ce05a14bb
The patch set beginning with commit: "ARM: ux500: Apply a ste-* prefix onto snowball.dts" thru commit: "ARM: ux500: Remove u9540.dts as it's been replaced" altered the names of the ux500 device tree files but forgot to: - Rename the ccu8540-pinctrl.dtsi file - Update #include statements from files using these files, so the build broke. - Update the Makefile for the device trees so the build broke. Fix it up so we can build them all again. Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
197 lines
3.6 KiB
Plaintext
197 lines
3.6 KiB
Plaintext
/*
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* Copyright 2012 ST-Ericsson
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ste-nomadik-pinctrl.dtsi"
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/ {
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soc {
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pinctrl {
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uart0 {
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uart0_default_mux: uart0_mux {
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default_mux {
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ste,function = "u0";
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ste,pins = "u0_a_1";
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};
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};
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uart0_default_mode: uart0_default {
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default_cfg1 {
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ste,pins = "GPIO0", "GPIO2";
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO1", "GPIO3";
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ste,config = <&out_hi>;
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};
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};
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uart0_sleep_mode: uart0_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO0", "GPIO2";
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ste,config = <&slpm_in_pu>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO1", "GPIO3";
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ste,config = <&slpm_out_hi>;
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};
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};
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};
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uart2 {
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uart2_default_mode: uart2_default {
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default_mux {
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ste,function = "u2";
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ste,pins = "u2txrx_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO120";
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO121";
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ste,config = <&out_hi>;
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};
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};
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uart2_sleep_mode: uart2_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO120";
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ste,config = <&slpm_in_pu>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO121";
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ste,config = <&slpm_out_hi>;
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};
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};
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};
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i2c0 {
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i2c0_default_mux: i2c_mux {
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default_mux {
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ste,function = "i2c0";
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ste,pins = "i2c0_a_1";
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};
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};
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i2c0_default_mode: i2c_default {
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default_cfg1 {
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ste,pins = "GPIO147", "GPIO148";
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ste,config = <&in_pu>;
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};
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};
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i2c0_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO147", "GPIO148";
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ste,config = <&slpm_in_pu>;
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};
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};
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};
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i2c1 {
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i2c1_default_mux: i2c_mux {
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default_mux {
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ste,function = "i2c1";
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ste,pins = "i2c1_b_2";
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};
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};
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i2c1_default_mode: i2c_default {
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default_cfg1 {
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ste,pins = "GPIO16", "GPIO17";
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ste,config = <&in_pu>;
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};
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};
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i2c1_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO16", "GPIO17";
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ste,config = <&slpm_in_pu>;
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};
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};
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};
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i2c2 {
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i2c2_default_mux: i2c_mux {
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default_mux {
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ste,function = "i2c2";
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ste,pins = "i2c2_b_2";
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};
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};
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i2c2_default_mode: i2c_default {
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default_cfg1 {
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ste,pins = "GPIO10", "GPIO11";
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ste,config = <&in_pu>;
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};
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};
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i2c2_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO11", "GPIO11";
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ste,config = <&slpm_in_pu>;
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};
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};
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};
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i2c4 {
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i2c4_default_mux: i2c_mux {
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default_mux {
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ste,function = "i2c4";
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ste,pins = "i2c4_b_2";
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};
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};
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i2c4_default_mode: i2c_default {
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default_cfg1 {
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ste,pins = "GPIO122", "GPIO123";
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ste,config = <&in_pu>;
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};
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};
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i2c4_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO122", "GPIO123";
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ste,config = <&slpm_in_pu>;
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};
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};
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};
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i2c5 {
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i2c5_default_mux: i2c_mux {
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default_mux {
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ste,function = "i2c5";
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ste,pins = "i2c5_c_2";
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};
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};
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i2c5_default_mode: i2c_default {
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default_cfg1 {
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ste,pins = "GPIO118", "GPIO119";
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ste,config = <&in_pu>;
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};
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};
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i2c5_sleep_mode: i2c_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO118", "GPIO119";
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ste,config = <&slpm_in_pu>;
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};
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};
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};
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};
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};
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};
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