119 lines
3.0 KiB
ArmAsm
119 lines
3.0 KiB
ArmAsm
/* arch/arm/mach-tegra/include/mach/entry-macro.S
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*
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* Copyright (C) 2009 Palm, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <mach/iomap.h>
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#include <mach/io.h>
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#if defined(CONFIG_ARM_GIC)
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#include <asm/hardware/gic.h>
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/* Uses the GIC interrupt controller built into the cpu */
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#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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movw \base, #(ICTRL_BASE & 0x0000ffff)
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movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Interrupts 0-15 are IPI
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* 16-28 are reserved
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* 29-31 are local. We allow 30 to be used for the watchdog.
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* For now, we ignore all local interrupts so only return an interrupt
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* if it's between 30 and 1020. The test_for_ipi routine below will
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* pick up on IPIs.
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*
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* A simple read from the controller will tell us the number of the
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* highest priority enabled interrupt. We then just need to check
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* whether it is in the valid range for an IRQ (30-1020 inclusive).
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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/* bits 12-10 = src CPU, 9-0 = int # */
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ldr \irqstat, [\base, #GIC_CPU_INTACK]
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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.endm
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt on the
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* controller, since this requires the original irqstat value which
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* we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved.. */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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#else
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/* legacy interrupt controller for AP16 */
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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@ enable imprecise aborts
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cpsie a
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@ EVP base at 0xf010f000
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mov \base, #0xf0000000
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orr \base, #0x00100000
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orr \base, #0x0000f000
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS
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cmp \irqnr, #0x80
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.endm
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#endif
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