6b54783620
If the divider or multiplier values are 0 in the register, bypassing the divider and returning the parent clock rate in clk_fd_recalc_rate(). Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed commitlog typo]
139 lines
3.1 KiB
C
139 lines
3.1 KiB
C
/*
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* Copyright (C) 2014 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adjustable fractional divider clock implementation.
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* Output rate = (m / n) * parent_rate.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/gcd.h>
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#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
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static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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u32 val, m, n;
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u64 ret;
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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val = clk_readl(fd->reg);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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m = (val & fd->mmask) >> fd->mshift;
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n = (val & fd->nmask) >> fd->nshift;
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if (!n || !m)
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return parent_rate;
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ret = (u64)parent_rate * m;
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do_div(ret, n);
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return ret;
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}
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static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned maxn = (fd->nmask >> fd->nshift) + 1;
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unsigned div;
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if (!rate || rate >= *prate)
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return *prate;
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div = gcd(*prate, rate);
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while ((*prate / div) > maxn) {
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div <<= 1;
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rate <<= 1;
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}
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return rate;
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}
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static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_fractional_divider *fd = to_clk_fd(hw);
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unsigned long flags = 0;
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unsigned long div;
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unsigned n, m;
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u32 val;
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div = gcd(parent_rate, rate);
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m = rate / div;
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n = parent_rate / div;
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if (fd->lock)
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spin_lock_irqsave(fd->lock, flags);
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val = clk_readl(fd->reg);
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val &= ~(fd->mmask | fd->nmask);
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val |= (m << fd->mshift) | (n << fd->nshift);
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clk_writel(val, fd->reg);
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if (fd->lock)
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spin_unlock_irqrestore(fd->lock, flags);
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return 0;
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}
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const struct clk_ops clk_fractional_divider_ops = {
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.recalc_rate = clk_fd_recalc_rate,
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.round_rate = clk_fd_round_rate,
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.set_rate = clk_fd_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
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struct clk *clk_register_fractional_divider(struct device *dev,
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const char *name, const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
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u8 clk_divider_flags, spinlock_t *lock)
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{
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struct clk_fractional_divider *fd;
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struct clk_init_data init;
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struct clk *clk;
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fd = kzalloc(sizeof(*fd), GFP_KERNEL);
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if (!fd) {
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dev_err(dev, "could not allocate fractional divider clk\n");
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &clk_fractional_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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fd->reg = reg;
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fd->mshift = mshift;
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fd->mmask = (BIT(mwidth) - 1) << mshift;
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fd->nshift = nshift;
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fd->nmask = (BIT(nwidth) - 1) << nshift;
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fd->flags = clk_divider_flags;
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fd->lock = lock;
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fd->hw.init = &init;
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clk = clk_register(dev, &fd->hw);
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if (IS_ERR(clk))
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kfree(fd);
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return clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_fractional_divider);
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