8cb51ba8e0
From NHM processor onward, Intel processors can support hardware accelerated CRC32c algorithm with the new CRC32 instruction in SSE 4.2 instruction set. The patch detects the availability of the feature, and chooses the most proper way to calculate CRC32c checksum. Byte code instructions are used for compiler compatibility. No MMX / XMM registers is involved in the implementation. Signed-off-by: Austin Zhang <austin.zhang@intel.com> Signed-off-by: Kent Liu <kent.liu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> |
||
|---|---|---|
| .. | ||
| Makefile | ||
| aes-i586-asm_32.S | ||
| aes-x86_64-asm_64.S | ||
| aes_glue.c | ||
| crc32c-intel.c | ||
| salsa20-i586-asm_32.S | ||
| salsa20-x86_64-asm_64.S | ||
| salsa20_glue.c | ||
| twofish-i586-asm_32.S | ||
| twofish-x86_64-asm_64.S | ||
| twofish_glue.c | ||