965 lines
22 KiB
C
965 lines
22 KiB
C
/*
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* Driver for it913x-fe Frontend
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*
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* with support for on chip it9137 integral tuner
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*
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* Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com)
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* IT9137 Copyright (C) ITE Tech Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include "dvb_frontend.h"
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#include "it913x-fe.h"
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#include "it913x-fe-priv.h"
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static int it913x_debug;
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module_param_named(debug, it913x_debug, int, 0644);
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MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
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#define dprintk(level, args...) do { \
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if (level & it913x_debug) \
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printk(KERN_DEBUG "it913x-fe: " args); \
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} while (0)
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#define deb_info(args...) dprintk(0x01, args)
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#define debug_data_snipet(level, name, p) \
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dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \
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*p, *(p+1), *(p+2), *(p+3), *(p+4), \
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*(p+5), *(p+6), *(p+7));
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#define info(format, arg...) \
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printk(KERN_INFO "it913x-fe: " format "\n" , ## arg)
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struct it913x_fe_state {
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struct dvb_frontend frontend;
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struct i2c_adapter *i2c_adap;
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struct ite_config *config;
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u8 i2c_addr;
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u32 frequency;
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fe_modulation_t constellation;
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fe_transmit_mode_t transmission_mode;
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u32 crystalFrequency;
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u32 adcFrequency;
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u8 tuner_type;
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struct adctable *table;
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fe_status_t it913x_status;
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u16 tun_xtal;
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u8 tun_fdiv;
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u8 tun_clk_mode;
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u32 tun_fn_min;
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};
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static int it913x_read_reg(struct it913x_fe_state *state,
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u32 reg, u8 *data, u8 count)
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{
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int ret;
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u8 pro = PRO_DMOD; /* All reads from demodulator */
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u8 b[4];
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struct i2c_msg msg[2] = {
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{ .addr = state->i2c_addr + (pro << 1), .flags = 0,
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.buf = b, .len = sizeof(b) },
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{ .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD,
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.buf = data, .len = count }
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};
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b[0] = (u8) reg >> 24;
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b[1] = (u8)(reg >> 16) & 0xff;
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b[2] = (u8)(reg >> 8) & 0xff;
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b[3] = (u8) reg & 0xff;
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ret = i2c_transfer(state->i2c_adap, msg, 2);
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return ret;
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}
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static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg)
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{
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int ret;
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u8 b[1];
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ret = it913x_read_reg(state, reg, &b[0], sizeof(b));
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return (ret < 0) ? -ENODEV : b[0];
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}
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static int it913x_write(struct it913x_fe_state *state,
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u8 pro, u32 reg, u8 buf[], u8 count)
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{
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u8 b[256];
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struct i2c_msg msg[1] = {
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{ .addr = state->i2c_addr + (pro << 1), .flags = 0,
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.buf = b, .len = count + 4 }
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};
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int ret;
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b[0] = (u8) reg >> 24;
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b[1] = (u8)(reg >> 16) & 0xff;
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b[2] = (u8)(reg >> 8) & 0xff;
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b[3] = (u8) reg & 0xff;
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memcpy(&b[4], buf, count);
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ret = i2c_transfer(state->i2c_adap, msg, 1);
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if (ret < 0)
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return -EIO;
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return 0;
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}
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static int it913x_write_reg(struct it913x_fe_state *state,
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u8 pro, u32 reg, u32 data)
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{
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int ret;
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u8 b[4];
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u8 s;
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b[0] = data >> 24;
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b[1] = (data >> 16) & 0xff;
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b[2] = (data >> 8) & 0xff;
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b[3] = data & 0xff;
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/* expand write as needed */
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if (data < 0x100)
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s = 3;
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else if (data < 0x1000)
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s = 2;
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else if (data < 0x100000)
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s = 1;
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else
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s = 0;
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ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s);
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return ret;
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}
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static int it913x_fe_script_loader(struct it913x_fe_state *state,
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struct it913xset *loadscript)
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{
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int ret, i;
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if (loadscript == NULL)
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return -EINVAL;
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for (i = 0; i < 1000; ++i) {
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if (loadscript[i].pro == 0xff)
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break;
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ret = it913x_write(state, loadscript[i].pro,
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loadscript[i].address,
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loadscript[i].reg, loadscript[i].count);
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if (ret < 0)
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return -ENODEV;
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}
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return 0;
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}
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static int it913x_init_tuner(struct it913x_fe_state *state)
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{
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int ret, i, reg;
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u8 val, nv_val;
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u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2};
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u8 b[2];
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reg = it913x_read_reg_u8(state, 0xec86);
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switch (reg) {
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case 0:
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state->tun_clk_mode = reg;
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state->tun_xtal = 2000;
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state->tun_fdiv = 3;
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val = 16;
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break;
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case -ENODEV:
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return -ENODEV;
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case 1:
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default:
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state->tun_clk_mode = reg;
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state->tun_xtal = 640;
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state->tun_fdiv = 1;
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val = 6;
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break;
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}
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reg = it913x_read_reg_u8(state, 0xed03);
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if (reg < 0)
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return -ENODEV;
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else if (reg < sizeof(nv))
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nv_val = nv[reg];
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else
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nv_val = 2;
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for (i = 0; i < 50; i++) {
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ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b));
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reg = (b[1] << 8) + b[0];
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if (reg > 0)
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break;
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if (ret < 0)
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return -ENODEV;
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udelay(2000);
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}
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state->tun_fn_min = state->tun_xtal * reg;
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state->tun_fn_min /= (state->tun_fdiv * nv_val);
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deb_info("Tuner fn_min %d", state->tun_fn_min);
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if (state->config->chip_ver > 1)
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msleep(50);
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else {
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for (i = 0; i < 50; i++) {
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reg = it913x_read_reg_u8(state, 0xec82);
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if (reg > 0)
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break;
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if (reg < 0)
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return -ENODEV;
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udelay(2000);
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}
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}
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return it913x_write_reg(state, PRO_DMOD, 0xed81, val);
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}
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static int it9137_set_tuner(struct it913x_fe_state *state,
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u32 bandwidth, u32 frequency_m)
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{
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struct it913xset *set_tuner = set_it9137_template;
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int ret, reg;
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u32 frequency = frequency_m / 1000;
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u32 freq, temp_f, tmp;
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u16 iqik_m_cal;
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u16 n_div;
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u8 n;
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u8 l_band;
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u8 lna_band;
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u8 bw;
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if (state->config->firmware_ver == 1)
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set_tuner = set_it9135_template;
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else
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set_tuner = set_it9137_template;
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deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth);
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if (frequency >= 51000 && frequency <= 440000) {
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l_band = 0;
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lna_band = 0;
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} else if (frequency > 440000 && frequency <= 484000) {
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l_band = 1;
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lna_band = 1;
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} else if (frequency > 484000 && frequency <= 533000) {
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l_band = 1;
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lna_band = 2;
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} else if (frequency > 533000 && frequency <= 587000) {
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l_band = 1;
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lna_band = 3;
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} else if (frequency > 587000 && frequency <= 645000) {
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l_band = 1;
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lna_band = 4;
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} else if (frequency > 645000 && frequency <= 710000) {
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l_band = 1;
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lna_band = 5;
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} else if (frequency > 710000 && frequency <= 782000) {
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l_band = 1;
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lna_band = 6;
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} else if (frequency > 782000 && frequency <= 860000) {
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l_band = 1;
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lna_band = 7;
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} else if (frequency > 1450000 && frequency <= 1492000) {
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l_band = 1;
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lna_band = 0;
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} else if (frequency > 1660000 && frequency <= 1685000) {
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l_band = 1;
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lna_band = 1;
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} else
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return -EINVAL;
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set_tuner[0].reg[0] = lna_band;
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switch (bandwidth) {
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case 5000000:
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bw = 0;
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break;
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case 6000000:
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bw = 2;
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break;
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case 7000000:
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bw = 4;
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break;
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default:
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case 8000000:
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bw = 6;
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break;
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}
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set_tuner[1].reg[0] = bw;
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set_tuner[2].reg[0] = 0xa0 | (l_band << 3);
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if (frequency > 53000 && frequency <= 74000) {
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n_div = 48;
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n = 0;
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} else if (frequency > 74000 && frequency <= 111000) {
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n_div = 32;
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n = 1;
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} else if (frequency > 111000 && frequency <= 148000) {
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n_div = 24;
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n = 2;
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} else if (frequency > 148000 && frequency <= 222000) {
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n_div = 16;
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n = 3;
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} else if (frequency > 222000 && frequency <= 296000) {
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n_div = 12;
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n = 4;
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} else if (frequency > 296000 && frequency <= 445000) {
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n_div = 8;
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n = 5;
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} else if (frequency > 445000 && frequency <= state->tun_fn_min) {
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n_div = 6;
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n = 6;
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} else if (frequency > state->tun_fn_min && frequency <= 950000) {
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n_div = 4;
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n = 7;
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} else if (frequency > 1450000 && frequency <= 1680000) {
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n_div = 2;
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n = 0;
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} else
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return -EINVAL;
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reg = it913x_read_reg_u8(state, 0xed81);
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iqik_m_cal = (u16)reg * n_div;
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if (reg < 0x20) {
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if (state->tun_clk_mode == 0)
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iqik_m_cal = (iqik_m_cal * 9) >> 5;
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else
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iqik_m_cal >>= 1;
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} else {
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iqik_m_cal = 0x40 - iqik_m_cal;
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if (state->tun_clk_mode == 0)
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iqik_m_cal = ~((iqik_m_cal * 9) >> 5);
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else
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iqik_m_cal = ~(iqik_m_cal >> 1);
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}
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temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv;
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freq = temp_f / state->tun_xtal;
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tmp = freq * state->tun_xtal;
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if ((temp_f - tmp) >= (state->tun_xtal >> 1))
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freq++;
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freq += (u32) n << 13;
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/* Frequency OMEGA_IQIK_M_CAL_MID*/
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temp_f = freq + (u32)iqik_m_cal;
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set_tuner[3].reg[0] = temp_f & 0xff;
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set_tuner[4].reg[0] = (temp_f >> 8) & 0xff;
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deb_info("High Frequency = %04x", temp_f);
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/* Lower frequency */
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set_tuner[5].reg[0] = freq & 0xff;
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set_tuner[6].reg[0] = (freq >> 8) & 0xff;
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deb_info("low Frequency = %04x", freq);
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ret = it913x_fe_script_loader(state, set_tuner);
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return (ret < 0) ? -ENODEV : 0;
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}
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static int it913x_fe_select_bw(struct it913x_fe_state *state,
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u32 bandwidth, u32 adcFrequency)
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{
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int ret, i;
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u8 buffer[256];
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u32 coeff[8];
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u16 bfsfcw_fftinx_ratio;
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u16 fftinx_bfsfcw_ratio;
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u8 count;
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u8 bw;
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u8 adcmultiplier;
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deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency);
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switch (bandwidth) {
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case 5000000:
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bw = 3;
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break;
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case 6000000:
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bw = 0;
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break;
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case 7000000:
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bw = 1;
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break;
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default:
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case 8000000:
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bw = 2;
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break;
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}
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ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw);
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if (state->table == NULL)
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return -EINVAL;
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/* In write order */
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coeff[0] = state->table[bw].coeff_1_2048;
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coeff[1] = state->table[bw].coeff_2_2k;
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coeff[2] = state->table[bw].coeff_1_8191;
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coeff[3] = state->table[bw].coeff_1_8192;
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coeff[4] = state->table[bw].coeff_1_8193;
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coeff[5] = state->table[bw].coeff_2_8k;
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coeff[6] = state->table[bw].coeff_1_4096;
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coeff[7] = state->table[bw].coeff_2_4k;
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bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio;
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fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio;
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/* ADC multiplier */
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ret = it913x_read_reg_u8(state, ADC_X_2);
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if (ret < 0)
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return -EINVAL;
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adcmultiplier = ret;
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count = 0;
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/* Build Buffer for COEFF Registers */
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for (i = 0; i < 8; i++) {
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if (adcmultiplier == 1)
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coeff[i] /= 2;
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buffer[count++] = (coeff[i] >> 24) & 0x3;
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buffer[count++] = (coeff[i] >> 16) & 0xff;
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buffer[count++] = (coeff[i] >> 8) & 0xff;
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buffer[count++] = coeff[i] & 0xff;
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}
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/* bfsfcw_fftinx_ratio register 0x21-0x22 */
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buffer[count++] = bfsfcw_fftinx_ratio & 0xff;
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buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff;
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/* fftinx_bfsfcw_ratio register 0x23-0x24 */
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buffer[count++] = fftinx_bfsfcw_ratio & 0xff;
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buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff;
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/* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/
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ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count);
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for (i = 0; i < 42; i += 8)
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debug_data_snipet(0x1, "Buffer", &buffer[i]);
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return ret;
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}
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static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status)
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{
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struct it913x_fe_state *state = fe->demodulator_priv;
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int ret, i;
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fe_status_t old_status = state->it913x_status;
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*status = 0;
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if (state->it913x_status == 0) {
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ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
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if (ret == 0x1) {
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*status |= FE_HAS_SIGNAL;
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for (i = 0; i < 40; i++) {
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ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK);
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if (ret == 0x1)
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break;
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msleep(25);
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}
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if (ret == 0x1)
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*status |= FE_HAS_CARRIER
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| FE_HAS_VITERBI
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| FE_HAS_SYNC;
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state->it913x_status = *status;
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}
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}
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if (state->it913x_status & FE_HAS_SYNC) {
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ret = it913x_read_reg_u8(state, TPSD_LOCK);
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if (ret == 0x1)
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*status |= FE_HAS_LOCK
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| state->it913x_status;
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else
|
|
state->it913x_status = 0;
|
|
if (old_status != state->it913x_status)
|
|
ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int it913x_fe_read_signal_strength(struct dvb_frontend *fe,
|
|
u16 *strength)
|
|
{
|
|
struct it913x_fe_state *state = fe->demodulator_priv;
|
|
int ret = it913x_read_reg_u8(state, SIGNAL_LEVEL);
|
|
/*SIGNAL_LEVEL always returns 100%! so using FE_HAS_SIGNAL as switch*/
|
|
if (state->it913x_status & FE_HAS_SIGNAL)
|
|
ret = (ret * 0xff) / 0x64;
|
|
else
|
|
ret = 0x0;
|
|
ret |= ret << 0x8;
|
|
*strength = ret;
|
|
return 0;
|
|
}
|
|
|
|
static int it913x_fe_read_snr(struct dvb_frontend *fe, u16 *snr)
|
|
{
|
|
struct it913x_fe_state *state = fe->demodulator_priv;
|
|
int ret;
|
|
u8 reg[3];
|
|
u32 snr_val, snr_min, snr_max;
|
|
u32 temp;
|
|
|
|
ret = it913x_read_reg(state, 0x2c, reg, sizeof(reg));
|
|
|
|
snr_val = (u32)(reg[2] << 16) | (reg[1] < 8) | reg[0];
|
|
|
|
ret |= it913x_read_reg(state, 0xf78b, reg, 1);
|
|
if (reg[0])
|
|
snr_val /= reg[0];
|
|
|
|
if (state->transmission_mode == TRANSMISSION_MODE_2K)
|
|
snr_val *= 4;
|
|
else if (state->transmission_mode == TRANSMISSION_MODE_4K)
|
|
snr_val *= 2;
|
|
|
|
if (state->constellation == QPSK) {
|
|
snr_min = 0xb4711;
|
|
snr_max = 0x191451;
|
|
} else if (state->constellation == QAM_16) {
|
|
snr_min = 0x4f0d5;
|
|
snr_max = 0xc7925;
|
|
} else if (state->constellation == QAM_64) {
|
|
snr_min = 0x256d0;
|
|
snr_max = 0x626be;
|
|
} else
|
|
return -EINVAL;
|
|
|
|
if (snr_val < snr_min)
|
|
*snr = 0;
|
|
else if (snr_val < snr_max) {
|
|
temp = (snr_val - snr_min) >> 5;
|
|
temp *= 0xffff;
|
|
temp /= (snr_max - snr_min) >> 5;
|
|
*snr = (u16)temp;
|
|
} else
|
|
*snr = 0xffff;
|
|
|
|
return (ret < 0) ? -ENODEV : 0;
|
|
}
|
|
|
|
static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
|
|
{
|
|
*ber = 0;
|
|
return 0;
|
|
}
|
|
|
|
static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
|
|
{
|
|
*ucblocks = 0;
|
|
return 0;
|
|
}
|
|
|
|
static int it913x_fe_get_frontend(struct dvb_frontend *fe,
|
|
struct dtv_frontend_properties *p)
|
|
{
|
|
struct it913x_fe_state *state = fe->demodulator_priv;
|
|
int ret;
|
|
u8 reg[8];
|
|
|
|
ret = it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg));
|
|
|
|
if (reg[3] < 3)
|
|
p->modulation = fe_con[reg[3]];
|
|
|
|
if (reg[0] < 3)
|
|
p->transmission_mode = fe_mode[reg[0]];
|
|
|
|
if (reg[1] < 4)
|
|
p->guard_interval = fe_gi[reg[1]];
|
|
|
|
if (reg[2] < 4)
|
|
p->hierarchy = fe_hi[reg[2]];
|
|
|
|
p->code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE;
|
|
p->code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE;
|
|
|
|
/* Update internal state to reflect the autodetected props */
|
|
state->constellation = p->modulation;
|
|
state->transmission_mode = p->transmission_mode;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int it913x_fe_set_frontend(struct dvb_frontend *fe)
|
|
{
|
|
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
|
|
struct it913x_fe_state *state = fe->demodulator_priv;
|
|
int ret, i;
|
|
u8 empty_ch, last_ch;
|
|
|
|
state->it913x_status = 0;
|
|
|
|
/* Set bw*/
|
|
ret = it913x_fe_select_bw(state, p->bandwidth_hz,
|
|
state->adcFrequency);
|
|
|
|
/* Training Mode Off */
|
|
ret = it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0);
|
|
|
|
/* Clear Empty Channel */
|
|
ret = it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0);
|
|
|
|
/* Clear bits */
|
|
ret = it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0);
|
|
/* LED on */
|
|
ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
|
|
/* Select Band*/
|
|
if ((p->frequency >= 51000000) && (p->frequency <= 230000000))
|
|
i = 0;
|
|
else if ((p->frequency >= 350000000) && (p->frequency <= 900000000))
|
|
i = 1;
|
|
else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000))
|
|
i = 2;
|
|
else
|
|
return -EOPNOTSUPP;
|
|
|
|
ret = it913x_write_reg(state, PRO_DMOD, FREE_BAND, i);
|
|
|
|
deb_info("Frontend Set Tuner Type %02x", state->tuner_type);
|
|
switch (state->tuner_type) {
|
|
case IT9135_38:
|
|
case IT9135_51:
|
|
case IT9135_52:
|
|
case IT9135_60:
|
|
case IT9135_61:
|
|
case IT9135_62:
|
|
ret = it9137_set_tuner(state,
|
|
p->bandwidth_hz, p->frequency);
|
|
break;
|
|
default:
|
|
if (fe->ops.tuner_ops.set_params) {
|
|
fe->ops.tuner_ops.set_params(fe);
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
fe->ops.i2c_gate_ctrl(fe, 0);
|
|
}
|
|
break;
|
|
}
|
|
/* LED off */
|
|
ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
|
|
/* Trigger ofsm */
|
|
ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
|
|
last_ch = 2;
|
|
for (i = 0; i < 40; ++i) {
|
|
empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
|
|
if (last_ch == 1 && empty_ch == 1)
|
|
break;
|
|
if (last_ch == 2 && empty_ch == 2)
|
|
return 0;
|
|
last_ch = empty_ch;
|
|
msleep(25);
|
|
}
|
|
for (i = 0; i < 40; ++i) {
|
|
if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1)
|
|
break;
|
|
msleep(25);
|
|
}
|
|
|
|
state->frequency = p->frequency;
|
|
return 0;
|
|
}
|
|
|
|
static int it913x_fe_suspend(struct it913x_fe_state *state)
|
|
{
|
|
int ret, i;
|
|
u8 b;
|
|
|
|
ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1);
|
|
|
|
ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
|
|
|
|
for (i = 0; i < 128; i++) {
|
|
ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1);
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
if (b == 0)
|
|
break;
|
|
|
|
}
|
|
|
|
ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8);
|
|
/* Turn LED off */
|
|
ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
|
|
|
|
ret |= it913x_fe_script_loader(state, it9137_tuner_off);
|
|
|
|
return (ret < 0) ? -ENODEV : 0;
|
|
}
|
|
|
|
/* Power sequence */
|
|
/* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */
|
|
/* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */
|
|
|
|
static int it913x_fe_sleep(struct dvb_frontend *fe)
|
|
{
|
|
struct it913x_fe_state *state = fe->demodulator_priv;
|
|
return it913x_fe_suspend(state);
|
|
}
|
|
|
|
static u32 compute_div(u32 a, u32 b, u32 x)
|
|
{
|
|
u32 res = 0;
|
|
u32 c = 0;
|
|
u32 i = 0;
|
|
|
|
if (a > b) {
|
|
c = a / b;
|
|
a = a - c * b;
|
|
}
|
|
|
|
for (i = 0; i < x; i++) {
|
|
if (a >= b) {
|
|
res += 1;
|
|
a -= b;
|
|
}
|
|
a <<= 1;
|
|
res <<= 1;
|
|
}
|
|
|
|
res = (c << x) + res;
|
|
|
|
return res;
|
|
}
|
|
|
|
static int it913x_fe_start(struct it913x_fe_state *state)
|
|
{
|
|
struct it913xset *set_lna;
|
|
struct it913xset *set_mode;
|
|
int ret;
|
|
u8 adf = (state->config->adf & 0xf);
|
|
u32 adc, xtal;
|
|
u8 b[4];
|
|
|
|
if (state->config->chip_ver == 1)
|
|
ret = it913x_init_tuner(state);
|
|
|
|
info("ADF table value :%02x", adf);
|
|
|
|
if (adf < 10) {
|
|
state->crystalFrequency = fe_clockTable[adf].xtal ;
|
|
state->table = fe_clockTable[adf].table;
|
|
state->adcFrequency = state->table->adcFrequency;
|
|
|
|
adc = compute_div(state->adcFrequency, 1000000ul, 19ul);
|
|
xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul);
|
|
|
|
} else
|
|
return -EINVAL;
|
|
|
|
/* Set LED indicator on GPIOH3 */
|
|
ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1);
|
|
ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1);
|
|
ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
|
|
|
|
ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type);
|
|
ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01);
|
|
ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01);
|
|
|
|
b[0] = xtal & 0xff;
|
|
b[1] = (xtal >> 8) & 0xff;
|
|
b[2] = (xtal >> 16) & 0xff;
|
|
b[3] = (xtal >> 24);
|
|
ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4);
|
|
|
|
b[0] = adc & 0xff;
|
|
b[1] = (adc >> 8) & 0xff;
|
|
b[2] = (adc >> 16) & 0xff;
|
|
ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3);
|
|
|
|
if (state->config->adc_x2)
|
|
ret |= it913x_write_reg(state, PRO_DMOD, ADC_X_2, 0x01);
|
|
b[0] = 0;
|
|
b[1] = 0;
|
|
b[2] = 0;
|
|
ret |= it913x_write(state, PRO_DMOD, 0x0029, b, 3);
|
|
|
|
info("Crystal Frequency :%d Adc Frequency :%d ADC X2: %02x",
|
|
state->crystalFrequency, state->adcFrequency,
|
|
state->config->adc_x2);
|
|
deb_info("Xtal value :%04x Adc value :%04x", xtal, adc);
|
|
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
/* v1 or v2 tuner script */
|
|
if (state->config->chip_ver > 1)
|
|
ret = it913x_fe_script_loader(state, it9135_v2);
|
|
else
|
|
ret = it913x_fe_script_loader(state, it9135_v1);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* LNA Scripts */
|
|
switch (state->tuner_type) {
|
|
case IT9135_51:
|
|
set_lna = it9135_51;
|
|
break;
|
|
case IT9135_52:
|
|
set_lna = it9135_52;
|
|
break;
|
|
case IT9135_60:
|
|
set_lna = it9135_60;
|
|
break;
|
|
case IT9135_61:
|
|
set_lna = it9135_61;
|
|
break;
|
|
case IT9135_62:
|
|
set_lna = it9135_62;
|
|
break;
|
|
case IT9135_38:
|
|
default:
|
|
set_lna = it9135_38;
|
|
}
|
|
info("Tuner LNA type :%02x", state->tuner_type);
|
|
|
|
ret = it913x_fe_script_loader(state, set_lna);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (state->config->chip_ver == 2) {
|
|
ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1);
|
|
ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0);
|
|
ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0);
|
|
ret |= it913x_init_tuner(state);
|
|
}
|
|
if (ret < 0)
|
|
return -ENODEV;
|
|
|
|
/* Always solo frontend */
|
|
set_mode = set_solo_fe;
|
|
ret |= it913x_fe_script_loader(state, set_mode);
|
|
|
|
ret |= it913x_fe_suspend(state);
|
|
return (ret < 0) ? -ENODEV : 0;
|
|
}
|
|
|
|
static int it913x_fe_init(struct dvb_frontend *fe)
|
|
{
|
|
struct it913x_fe_state *state = fe->demodulator_priv;
|
|
int ret = 0;
|
|
/* Power Up Tuner - common all versions */
|
|
ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1);
|
|
|
|
ret |= it913x_fe_script_loader(state, init_1);
|
|
|
|
ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0);
|
|
|
|
ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0);
|
|
|
|
return (ret < 0) ? -ENODEV : 0;
|
|
}
|
|
|
|
static void it913x_fe_release(struct dvb_frontend *fe)
|
|
{
|
|
struct it913x_fe_state *state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
static struct dvb_frontend_ops it913x_fe_ofdm_ops;
|
|
|
|
struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
|
|
u8 i2c_addr, struct ite_config *config)
|
|
{
|
|
struct it913x_fe_state *state = NULL;
|
|
int ret;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
return NULL;
|
|
if (config == NULL)
|
|
goto error;
|
|
|
|
state->i2c_adap = i2c_adap;
|
|
state->i2c_addr = i2c_addr;
|
|
state->config = config;
|
|
|
|
switch (state->config->tuner_id_0) {
|
|
case IT9135_51:
|
|
case IT9135_52:
|
|
case IT9135_60:
|
|
case IT9135_61:
|
|
case IT9135_62:
|
|
state->tuner_type = state->config->tuner_id_0;
|
|
break;
|
|
default:
|
|
case IT9135_38:
|
|
state->tuner_type = IT9135_38;
|
|
}
|
|
|
|
ret = it913x_fe_start(state);
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops,
|
|
sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
|
|
return &state->frontend;
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(it913x_fe_attach);
|
|
|
|
static struct dvb_frontend_ops it913x_fe_ofdm_ops = {
|
|
.delsys = { SYS_DVBT },
|
|
.info = {
|
|
.name = "it913x-fe DVB-T",
|
|
.type = FE_OFDM,
|
|
.frequency_min = 51000000,
|
|
.frequency_max = 1680000000,
|
|
.frequency_stepsize = 62500,
|
|
.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
|
|
FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
|
|
FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
|
|
FE_CAN_TRANSMISSION_MODE_AUTO |
|
|
FE_CAN_GUARD_INTERVAL_AUTO |
|
|
FE_CAN_HIERARCHY_AUTO,
|
|
},
|
|
|
|
.release = it913x_fe_release,
|
|
|
|
.init = it913x_fe_init,
|
|
.sleep = it913x_fe_sleep,
|
|
|
|
.set_frontend = it913x_fe_set_frontend,
|
|
.get_frontend = it913x_fe_get_frontend,
|
|
|
|
.read_status = it913x_fe_read_status,
|
|
.read_signal_strength = it913x_fe_read_signal_strength,
|
|
.read_snr = it913x_fe_read_snr,
|
|
.read_ber = it913x_fe_read_ber,
|
|
.read_ucblocks = it913x_fe_read_ucblocks,
|
|
};
|
|
|
|
MODULE_DESCRIPTION("it913x Frontend and it9137 tuner");
|
|
MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
|
|
MODULE_VERSION("1.12");
|
|
MODULE_LICENSE("GPL");
|