949 lines
25 KiB
C
949 lines
25 KiB
C
/*
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* linux/drivers/ide/ide-dma.c Version 4.10 June 9, 2000
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*
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* Copyright (c) 1999-2000 Andre Hedrick <andre@linux-ide.org>
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* May be copied or modified under the terms of the GNU General Public License
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*/
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/*
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* Special Thanks to Mark for his Six years of work.
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*
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* Copyright (c) 1995-1998 Mark Lord
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* May be copied or modified under the terms of the GNU General Public License
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*/
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/*
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* This module provides support for the bus-master IDE DMA functions
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* of various PCI chipsets, including the Intel PIIX (i82371FB for
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* the 430 FX chipset), the PIIX3 (i82371SB for the 430 HX/VX and
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* 440 chipsets), and the PIIX4 (i82371AB for the 430 TX chipset)
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* ("PIIX" stands for "PCI ISA IDE Xcellerator").
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*
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* Pretty much the same code works for other IDE PCI bus-mastering chipsets.
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*
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* DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
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*
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* By default, DMA support is prepared for use, but is currently enabled only
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* for drives which already have DMA enabled (UltraDMA or mode 2 multi/single),
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* or which are recognized as "good" (see table below). Drives with only mode0
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* or mode1 (multi/single) DMA should also work with this chipset/driver
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* (eg. MC2112A) but are not enabled by default.
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*
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* Use "hdparm -i" to view modes supported by a given drive.
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*
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* The hdparm-3.5 (or later) utility can be used for manually enabling/disabling
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* DMA support, but must be (re-)compiled against this kernel version or later.
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*
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* To enable DMA, use "hdparm -d1 /dev/hd?" on a per-drive basis after booting.
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* If problems arise, ide.c will disable DMA operation after a few retries.
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* This error recovery mechanism works and has been extremely well exercised.
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*
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* IDE drives, depending on their vintage, may support several different modes
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* of DMA operation. The boot-time modes are indicated with a "*" in
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* the "hdparm -i" listing, and can be changed with *knowledgeable* use of
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* the "hdparm -X" feature. There is seldom a need to do this, as drives
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* normally power-up with their "best" PIO/DMA modes enabled.
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*
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* Testing has been done with a rather extensive number of drives,
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* with Quantum & Western Digital models generally outperforming the pack,
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* and Fujitsu & Conner (and some Seagate which are really Conner) drives
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* showing more lackluster throughput.
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*
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* Keep an eye on /var/adm/messages for "DMA disabled" messages.
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*
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* Some people have reported trouble with Intel Zappa motherboards.
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* This can be fixed by upgrading the AMI BIOS to version 1.00.04.BS0,
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* available from ftp://ftp.intel.com/pub/bios/10004bs0.exe
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* (thanks to Glen Morrell <glen@spin.Stanford.edu> for researching this).
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*
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* Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
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* fixing the problem with the BIOS on some Acer motherboards.
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*
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* Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
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* "TX" chipset compatibility and for providing patches for the "TX" chipset.
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*
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* Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
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* at generic DMA -- his patches were referred to when preparing this code.
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*
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* Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
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* for supplying a Promise UDMA board & WD UDMA drive for this work!
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*
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* And, yes, Intel Zappa boards really *do* use both PIIX IDE ports.
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*
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* ATA-66/100 and recovery functions, I forgot the rest......
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/timer.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ide.h>
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#include <linux/delay.h>
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#include <linux/scatterlist.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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static const struct drive_list_entry drive_whitelist [] = {
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{ "Micropolis 2112A" , "ALL" },
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{ "CONNER CTMA 4000" , "ALL" },
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{ "CONNER CTT8000-A" , "ALL" },
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{ "ST34342A" , "ALL" },
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{ NULL , NULL }
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};
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static const struct drive_list_entry drive_blacklist [] = {
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{ "WDC AC11000H" , "ALL" },
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{ "WDC AC22100H" , "ALL" },
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{ "WDC AC32500H" , "ALL" },
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{ "WDC AC33100H" , "ALL" },
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{ "WDC AC31600H" , "ALL" },
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{ "WDC AC32100H" , "24.09P07" },
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{ "WDC AC23200L" , "21.10N21" },
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{ "Compaq CRD-8241B" , "ALL" },
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{ "CRD-8400B" , "ALL" },
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{ "CRD-8480B", "ALL" },
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{ "CRD-8482B", "ALL" },
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{ "CRD-84" , "ALL" },
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{ "SanDisk SDP3B" , "ALL" },
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{ "SanDisk SDP3B-64" , "ALL" },
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{ "SANYO CD-ROM CRD" , "ALL" },
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{ "HITACHI CDR-8" , "ALL" },
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{ "HITACHI CDR-8335" , "ALL" },
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{ "HITACHI CDR-8435" , "ALL" },
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{ "Toshiba CD-ROM XM-6202B" , "ALL" },
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{ "CD-532E-A" , "ALL" },
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{ "E-IDE CD-ROM CR-840", "ALL" },
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{ "CD-ROM Drive/F5A", "ALL" },
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{ "WPI CDD-820", "ALL" },
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{ "SAMSUNG CD-ROM SC-148C", "ALL" },
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{ "SAMSUNG CD-ROM SC", "ALL" },
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{ "SanDisk SDP3B-64" , "ALL" },
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{ "ATAPI CD-ROM DRIVE 40X MAXIMUM", "ALL" },
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{ "_NEC DV5800A", "ALL" },
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{ NULL , NULL }
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};
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/**
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* ide_in_drive_list - look for drive in black/white list
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* @id: drive identifier
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* @drive_table: list to inspect
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*
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* Look for a drive in the blacklist and the whitelist tables
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* Returns 1 if the drive is found in the table.
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*/
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int ide_in_drive_list(struct hd_driveid *id, const struct drive_list_entry *drive_table)
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{
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for ( ; drive_table->id_model ; drive_table++)
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if ((!strcmp(drive_table->id_model, id->model)) &&
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((strstr(id->fw_rev, drive_table->id_firmware)) ||
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(!strcmp(drive_table->id_firmware, "ALL"))))
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return 1;
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return 0;
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}
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/**
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* ide_dma_intr - IDE DMA interrupt handler
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* @drive: the drive the interrupt is for
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*
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* Handle an interrupt completing a read/write DMA transfer on an
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* IDE device
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*/
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ide_startstop_t ide_dma_intr (ide_drive_t *drive)
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{
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u8 stat = 0, dma_stat = 0;
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dma_stat = HWIF(drive)->ide_dma_end(drive);
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stat = HWIF(drive)->INB(IDE_STATUS_REG); /* get drive status */
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if (OK_STAT(stat,DRIVE_READY,drive->bad_wstat|DRQ_STAT)) {
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if (!dma_stat) {
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struct request *rq = HWGROUP(drive)->rq;
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if (rq->rq_disk) {
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ide_driver_t *drv;
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drv = *(ide_driver_t **)rq->rq_disk->private_data;
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drv->end_request(drive, 1, rq->nr_sectors);
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} else
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ide_end_request(drive, 1, rq->nr_sectors);
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return ide_stopped;
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}
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printk(KERN_ERR "%s: dma_intr: bad DMA status (dma_stat=%x)\n",
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drive->name, dma_stat);
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}
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return ide_error(drive, "dma_intr", stat);
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}
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EXPORT_SYMBOL_GPL(ide_dma_intr);
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#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
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/**
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* ide_build_sglist - map IDE scatter gather for DMA I/O
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* @drive: the drive to build the DMA table for
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* @rq: the request holding the sg list
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*
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* Perform the PCI mapping magic necessary to access the source or
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* target buffers of a request via PCI DMA. The lower layers of the
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* kernel provide the necessary cache management so that we can
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* operate in a portable fashion
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*/
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int ide_build_sglist(ide_drive_t *drive, struct request *rq)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct scatterlist *sg = hwif->sg_table;
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BUG_ON((rq->cmd_type == REQ_TYPE_ATA_TASKFILE) && rq->nr_sectors > 256);
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ide_map_sg(drive, rq);
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if (rq_data_dir(rq) == READ)
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hwif->sg_dma_direction = PCI_DMA_FROMDEVICE;
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else
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hwif->sg_dma_direction = PCI_DMA_TODEVICE;
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return pci_map_sg(hwif->pci_dev, sg, hwif->sg_nents, hwif->sg_dma_direction);
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}
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EXPORT_SYMBOL_GPL(ide_build_sglist);
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/**
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* ide_build_dmatable - build IDE DMA table
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*
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* ide_build_dmatable() prepares a dma request. We map the command
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* to get the pci bus addresses of the buffers and then build up
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* the PRD table that the IDE layer wants to be fed. The code
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* knows about the 64K wrap bug in the CS5530.
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*
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* Returns the number of built PRD entries if all went okay,
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* returns 0 otherwise.
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*
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* May also be invoked from trm290.c
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*/
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int ide_build_dmatable (ide_drive_t *drive, struct request *rq)
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{
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ide_hwif_t *hwif = HWIF(drive);
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unsigned int *table = hwif->dmatable_cpu;
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unsigned int is_trm290 = (hwif->chipset == ide_trm290) ? 1 : 0;
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unsigned int count = 0;
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int i;
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struct scatterlist *sg;
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hwif->sg_nents = i = ide_build_sglist(drive, rq);
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if (!i)
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return 0;
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sg = hwif->sg_table;
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while (i) {
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u32 cur_addr;
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u32 cur_len;
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cur_addr = sg_dma_address(sg);
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cur_len = sg_dma_len(sg);
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/*
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* Fill in the dma table, without crossing any 64kB boundaries.
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* Most hardware requires 16-bit alignment of all blocks,
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* but the trm290 requires 32-bit alignment.
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*/
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while (cur_len) {
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if (count++ >= PRD_ENTRIES) {
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printk(KERN_ERR "%s: DMA table too small\n", drive->name);
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goto use_pio_instead;
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} else {
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u32 xcount, bcount = 0x10000 - (cur_addr & 0xffff);
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if (bcount > cur_len)
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bcount = cur_len;
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*table++ = cpu_to_le32(cur_addr);
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xcount = bcount & 0xffff;
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if (is_trm290)
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xcount = ((xcount >> 2) - 1) << 16;
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if (xcount == 0x0000) {
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/*
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* Most chipsets correctly interpret a length of 0x0000 as 64KB,
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* but at least one (e.g. CS5530) misinterprets it as zero (!).
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* So here we break the 64KB entry into two 32KB entries instead.
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*/
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if (count++ >= PRD_ENTRIES) {
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printk(KERN_ERR "%s: DMA table too small\n", drive->name);
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goto use_pio_instead;
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}
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*table++ = cpu_to_le32(0x8000);
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*table++ = cpu_to_le32(cur_addr + 0x8000);
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xcount = 0x8000;
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}
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*table++ = cpu_to_le32(xcount);
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cur_addr += bcount;
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cur_len -= bcount;
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}
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}
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sg++;
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i--;
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}
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if (count) {
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if (!is_trm290)
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*--table |= cpu_to_le32(0x80000000);
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return count;
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}
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printk(KERN_ERR "%s: empty DMA table?\n", drive->name);
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use_pio_instead:
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pci_unmap_sg(hwif->pci_dev,
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hwif->sg_table,
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hwif->sg_nents,
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hwif->sg_dma_direction);
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return 0; /* revert to PIO for this request */
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}
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EXPORT_SYMBOL_GPL(ide_build_dmatable);
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/**
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* ide_destroy_dmatable - clean up DMA mapping
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* @drive: The drive to unmap
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*
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* Teardown mappings after DMA has completed. This must be called
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* after the completion of each use of ide_build_dmatable and before
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* the next use of ide_build_dmatable. Failure to do so will cause
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* an oops as only one mapping can be live for each target at a given
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* time.
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*/
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void ide_destroy_dmatable (ide_drive_t *drive)
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{
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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struct scatterlist *sg = HWIF(drive)->sg_table;
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int nents = HWIF(drive)->sg_nents;
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pci_unmap_sg(dev, sg, nents, HWIF(drive)->sg_dma_direction);
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}
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EXPORT_SYMBOL_GPL(ide_destroy_dmatable);
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/**
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* config_drive_for_dma - attempt to activate IDE DMA
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* @drive: the drive to place in DMA mode
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*
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* If the drive supports at least mode 2 DMA or UDMA of any kind
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* then attempt to place it into DMA mode. Drives that are known to
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* support DMA but predate the DMA properties or that are known
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* to have DMA handling bugs are also set up appropriately based
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* on the good/bad drive lists.
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*/
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static int config_drive_for_dma (ide_drive_t *drive)
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{
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struct hd_driveid *id = drive->id;
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ide_hwif_t *hwif = HWIF(drive);
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if ((id->capability & 1) && hwif->autodma) {
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/*
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* Enable DMA on any drive that has
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* UltraDMA (mode 0/1/2/3/4/5/6) enabled
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*/
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if ((id->field_valid & 4) && ((id->dma_ultra >> 8) & 0x7f))
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return hwif->ide_dma_on(drive);
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/*
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* Enable DMA on any drive that has mode2 DMA
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* (multi or single) enabled
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*/
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if (id->field_valid & 2) /* regular DMA */
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if ((id->dma_mword & 0x404) == 0x404 ||
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(id->dma_1word & 0x404) == 0x404)
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return hwif->ide_dma_on(drive);
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/* Consult the list of known "good" drives */
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if (__ide_dma_good_drive(drive))
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return hwif->ide_dma_on(drive);
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}
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// if (hwif->tuneproc != NULL) hwif->tuneproc(drive, 255);
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return hwif->ide_dma_off_quietly(drive);
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}
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/**
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* dma_timer_expiry - handle a DMA timeout
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* @drive: Drive that timed out
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*
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* An IDE DMA transfer timed out. In the event of an error we ask
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* the driver to resolve the problem, if a DMA transfer is still
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* in progress we continue to wait (arguably we need to add a
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* secondary 'I don't care what the drive thinks' timeout here)
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* Finally if we have an interrupt we let it complete the I/O.
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* But only one time - we clear expiry and if it's still not
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* completed after WAIT_CMD, we error and retry in PIO.
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* This can occur if an interrupt is lost or due to hang or bugs.
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*/
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static int dma_timer_expiry (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u8 dma_stat = hwif->INB(hwif->dma_status);
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printk(KERN_WARNING "%s: dma_timer_expiry: dma status == 0x%02x\n",
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drive->name, dma_stat);
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if ((dma_stat & 0x18) == 0x18) /* BUSY Stupid Early Timer !! */
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return WAIT_CMD;
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HWGROUP(drive)->expiry = NULL; /* one free ride for now */
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/* 1 dmaing, 2 error, 4 intr */
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if (dma_stat & 2) /* ERROR */
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return -1;
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if (dma_stat & 1) /* DMAing */
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return WAIT_CMD;
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if (dma_stat & 4) /* Got an Interrupt */
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return WAIT_CMD;
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return 0; /* Status is unknown -- reset the bus */
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}
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/**
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* __ide_dma_host_off - Generic DMA kill
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* @drive: drive to control
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*
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* Perform the generic IDE controller DMA off operation. This
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* works for most IDE bus mastering controllers
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*/
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int __ide_dma_host_off (ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u8 unit = (drive->select.b.unit & 0x01);
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u8 dma_stat = hwif->INB(hwif->dma_status);
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hwif->OUTB((dma_stat & ~(1<<(5+unit))), hwif->dma_status);
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return 0;
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}
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EXPORT_SYMBOL(__ide_dma_host_off);
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/**
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* __ide_dma_host_off_quietly - Generic DMA kill
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* @drive: drive to control
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*
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* Turn off the current DMA on this IDE controller.
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*/
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int __ide_dma_off_quietly (ide_drive_t *drive)
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{
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drive->using_dma = 0;
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ide_toggle_bounce(drive, 0);
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if (HWIF(drive)->ide_dma_host_off(drive))
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return 1;
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return 0;
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}
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EXPORT_SYMBOL(__ide_dma_off_quietly);
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#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
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|
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/**
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* __ide_dma_off - disable DMA on a device
|
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* @drive: drive to disable DMA on
|
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*
|
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* Disable IDE DMA for a device on this IDE controller.
|
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* Inform the user that DMA has been disabled.
|
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*/
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|
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int __ide_dma_off (ide_drive_t *drive)
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{
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printk(KERN_INFO "%s: DMA disabled\n", drive->name);
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return HWIF(drive)->ide_dma_off_quietly(drive);
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}
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|
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EXPORT_SYMBOL(__ide_dma_off);
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|
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#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
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/**
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* __ide_dma_host_on - Enable DMA on a host
|
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* @drive: drive to enable for DMA
|
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*
|
|
* Enable DMA on an IDE controller following generic bus mastering
|
|
* IDE controller behaviour
|
|
*/
|
|
|
|
int __ide_dma_host_on (ide_drive_t *drive)
|
|
{
|
|
if (drive->using_dma) {
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
u8 unit = (drive->select.b.unit & 0x01);
|
|
u8 dma_stat = hwif->INB(hwif->dma_status);
|
|
|
|
hwif->OUTB((dma_stat|(1<<(5+unit))), hwif->dma_status);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_host_on);
|
|
|
|
/**
|
|
* __ide_dma_on - Enable DMA on a device
|
|
* @drive: drive to enable DMA on
|
|
*
|
|
* Enable IDE DMA for a device on this IDE controller.
|
|
*/
|
|
|
|
int __ide_dma_on (ide_drive_t *drive)
|
|
{
|
|
/* consult the list of known "bad" drives */
|
|
if (__ide_dma_bad_drive(drive))
|
|
return 1;
|
|
|
|
drive->using_dma = 1;
|
|
ide_toggle_bounce(drive, 1);
|
|
|
|
if (HWIF(drive)->ide_dma_host_on(drive))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_on);
|
|
|
|
/**
|
|
* __ide_dma_check - check DMA setup
|
|
* @drive: drive to check
|
|
*
|
|
* Don't use - due for extermination
|
|
*/
|
|
|
|
int __ide_dma_check (ide_drive_t *drive)
|
|
{
|
|
return config_drive_for_dma(drive);
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_check);
|
|
|
|
/**
|
|
* ide_dma_setup - begin a DMA phase
|
|
* @drive: target device
|
|
*
|
|
* Build an IDE DMA PRD (IDE speak for scatter gather table)
|
|
* and then set up the DMA transfer registers for a device
|
|
* that follows generic IDE PCI DMA behaviour. Controllers can
|
|
* override this function if they need to
|
|
*
|
|
* Returns 0 on success. If a PIO fallback is required then 1
|
|
* is returned.
|
|
*/
|
|
|
|
int ide_dma_setup(ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
struct request *rq = HWGROUP(drive)->rq;
|
|
unsigned int reading;
|
|
u8 dma_stat;
|
|
|
|
if (rq_data_dir(rq))
|
|
reading = 0;
|
|
else
|
|
reading = 1 << 3;
|
|
|
|
/* fall back to pio! */
|
|
if (!ide_build_dmatable(drive, rq)) {
|
|
ide_map_sg(drive, rq);
|
|
return 1;
|
|
}
|
|
|
|
/* PRD table */
|
|
hwif->OUTL(hwif->dmatable_dma, hwif->dma_prdtable);
|
|
|
|
/* specify r/w */
|
|
hwif->OUTB(reading, hwif->dma_command);
|
|
|
|
/* read dma_status for INTR & ERROR flags */
|
|
dma_stat = hwif->INB(hwif->dma_status);
|
|
|
|
/* clear INTR & ERROR flags */
|
|
hwif->OUTB(dma_stat|6, hwif->dma_status);
|
|
drive->waiting_for_dma = 1;
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_dma_setup);
|
|
|
|
static void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
|
|
{
|
|
/* issue cmd to drive */
|
|
ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, dma_timer_expiry);
|
|
}
|
|
|
|
void ide_dma_start(ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
u8 dma_cmd = hwif->INB(hwif->dma_command);
|
|
|
|
/* Note that this is done *after* the cmd has
|
|
* been issued to the drive, as per the BM-IDE spec.
|
|
* The Promise Ultra33 doesn't work correctly when
|
|
* we do this part before issuing the drive cmd.
|
|
*/
|
|
/* start DMA */
|
|
hwif->OUTB(dma_cmd|1, hwif->dma_command);
|
|
hwif->dma = 1;
|
|
wmb();
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_dma_start);
|
|
|
|
/* returns 1 on error, 0 otherwise */
|
|
int __ide_dma_end (ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
u8 dma_stat = 0, dma_cmd = 0;
|
|
|
|
drive->waiting_for_dma = 0;
|
|
/* get dma_command mode */
|
|
dma_cmd = hwif->INB(hwif->dma_command);
|
|
/* stop DMA */
|
|
hwif->OUTB(dma_cmd&~1, hwif->dma_command);
|
|
/* get DMA status */
|
|
dma_stat = hwif->INB(hwif->dma_status);
|
|
/* clear the INTR & ERROR bits */
|
|
hwif->OUTB(dma_stat|6, hwif->dma_status);
|
|
/* purge DMA mappings */
|
|
ide_destroy_dmatable(drive);
|
|
/* verify good DMA status */
|
|
hwif->dma = 0;
|
|
wmb();
|
|
return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_end);
|
|
|
|
/* returns 1 if dma irq issued, 0 otherwise */
|
|
static int __ide_dma_test_irq(ide_drive_t *drive)
|
|
{
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
u8 dma_stat = hwif->INB(hwif->dma_status);
|
|
|
|
#if 0 /* do not set unless you know what you are doing */
|
|
if (dma_stat & 4) {
|
|
u8 stat = hwif->INB(IDE_STATUS_REG);
|
|
hwif->OUTB(hwif->dma_status, dma_stat & 0xE4);
|
|
}
|
|
#endif
|
|
/* return 1 if INTR asserted */
|
|
if ((dma_stat & 4) == 4)
|
|
return 1;
|
|
if (!drive->waiting_for_dma)
|
|
printk(KERN_WARNING "%s: (%s) called while not waiting\n",
|
|
drive->name, __FUNCTION__);
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
|
|
|
|
int __ide_dma_bad_drive (ide_drive_t *drive)
|
|
{
|
|
struct hd_driveid *id = drive->id;
|
|
|
|
int blacklist = ide_in_drive_list(id, drive_blacklist);
|
|
if (blacklist) {
|
|
printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
|
|
drive->name, id->model);
|
|
return blacklist;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_bad_drive);
|
|
|
|
int __ide_dma_good_drive (ide_drive_t *drive)
|
|
{
|
|
struct hd_driveid *id = drive->id;
|
|
return ide_in_drive_list(id, drive_whitelist);
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_good_drive);
|
|
|
|
int ide_use_dma(ide_drive_t *drive)
|
|
{
|
|
struct hd_driveid *id = drive->id;
|
|
ide_hwif_t *hwif = drive->hwif;
|
|
|
|
/* consult the list of known "bad" drives */
|
|
if (__ide_dma_bad_drive(drive))
|
|
return 0;
|
|
|
|
/* capable of UltraDMA modes */
|
|
if (id->field_valid & 4) {
|
|
if (hwif->ultra_mask & id->dma_ultra)
|
|
return 1;
|
|
}
|
|
|
|
/* capable of regular DMA modes */
|
|
if (id->field_valid & 2) {
|
|
if (hwif->mwdma_mask & id->dma_mword)
|
|
return 1;
|
|
if (hwif->swdma_mask & id->dma_1word)
|
|
return 1;
|
|
}
|
|
|
|
/* consult the list of known "good" drives */
|
|
if (__ide_dma_good_drive(drive) && id->eide_dma_time < 150)
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_use_dma);
|
|
|
|
void ide_dma_verbose(ide_drive_t *drive)
|
|
{
|
|
struct hd_driveid *id = drive->id;
|
|
ide_hwif_t *hwif = HWIF(drive);
|
|
|
|
if (id->field_valid & 4) {
|
|
if ((id->dma_ultra >> 8) && (id->dma_mword >> 8))
|
|
goto bug_dma_off;
|
|
if (id->dma_ultra & ((id->dma_ultra >> 8) & hwif->ultra_mask)) {
|
|
if (((id->dma_ultra >> 11) & 0x1F) &&
|
|
eighty_ninty_three(drive)) {
|
|
if ((id->dma_ultra >> 15) & 1) {
|
|
printk(", UDMA(mode 7)");
|
|
} else if ((id->dma_ultra >> 14) & 1) {
|
|
printk(", UDMA(133)");
|
|
} else if ((id->dma_ultra >> 13) & 1) {
|
|
printk(", UDMA(100)");
|
|
} else if ((id->dma_ultra >> 12) & 1) {
|
|
printk(", UDMA(66)");
|
|
} else if ((id->dma_ultra >> 11) & 1) {
|
|
printk(", UDMA(44)");
|
|
} else
|
|
goto mode_two;
|
|
} else {
|
|
mode_two:
|
|
if ((id->dma_ultra >> 10) & 1) {
|
|
printk(", UDMA(33)");
|
|
} else if ((id->dma_ultra >> 9) & 1) {
|
|
printk(", UDMA(25)");
|
|
} else if ((id->dma_ultra >> 8) & 1) {
|
|
printk(", UDMA(16)");
|
|
}
|
|
}
|
|
} else {
|
|
printk(", (U)DMA"); /* Can be BIOS-enabled! */
|
|
}
|
|
} else if (id->field_valid & 2) {
|
|
if ((id->dma_mword >> 8) && (id->dma_1word >> 8))
|
|
goto bug_dma_off;
|
|
printk(", DMA");
|
|
} else if (id->field_valid & 1) {
|
|
goto bug_dma_off;
|
|
}
|
|
return;
|
|
bug_dma_off:
|
|
printk(", BUG DMA OFF");
|
|
hwif->ide_dma_off_quietly(drive);
|
|
return;
|
|
}
|
|
|
|
EXPORT_SYMBOL(ide_dma_verbose);
|
|
|
|
#ifdef CONFIG_BLK_DEV_IDEDMA_PCI
|
|
int __ide_dma_lostirq (ide_drive_t *drive)
|
|
{
|
|
printk("%s: DMA interrupt recovery\n", drive->name);
|
|
return 1;
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_lostirq);
|
|
|
|
int __ide_dma_timeout (ide_drive_t *drive)
|
|
{
|
|
printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
|
|
if (HWIF(drive)->ide_dma_test_irq(drive))
|
|
return 0;
|
|
|
|
return HWIF(drive)->ide_dma_end(drive);
|
|
}
|
|
|
|
EXPORT_SYMBOL(__ide_dma_timeout);
|
|
|
|
/*
|
|
* Needed for allowing full modular support of ide-driver
|
|
*/
|
|
static int ide_release_dma_engine(ide_hwif_t *hwif)
|
|
{
|
|
if (hwif->dmatable_cpu) {
|
|
pci_free_consistent(hwif->pci_dev,
|
|
PRD_ENTRIES * PRD_BYTES,
|
|
hwif->dmatable_cpu,
|
|
hwif->dmatable_dma);
|
|
hwif->dmatable_cpu = NULL;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int ide_release_iomio_dma(ide_hwif_t *hwif)
|
|
{
|
|
release_region(hwif->dma_base, 8);
|
|
if (hwif->extra_ports)
|
|
release_region(hwif->extra_base, hwif->extra_ports);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Needed for allowing full modular support of ide-driver
|
|
*/
|
|
int ide_release_dma(ide_hwif_t *hwif)
|
|
{
|
|
ide_release_dma_engine(hwif);
|
|
|
|
if (hwif->mmio == 2)
|
|
return 1;
|
|
else
|
|
return ide_release_iomio_dma(hwif);
|
|
}
|
|
|
|
static int ide_allocate_dma_engine(ide_hwif_t *hwif)
|
|
{
|
|
hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
|
|
PRD_ENTRIES * PRD_BYTES,
|
|
&hwif->dmatable_dma);
|
|
|
|
if (hwif->dmatable_cpu)
|
|
return 0;
|
|
|
|
printk(KERN_ERR "%s: -- Error, unable to allocate DMA table.\n",
|
|
hwif->cds->name);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int ide_mapped_mmio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
|
|
{
|
|
printk(KERN_INFO " %s: MMIO-DMA ", hwif->name);
|
|
|
|
hwif->dma_base = base;
|
|
|
|
if(hwif->mate)
|
|
hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base : base;
|
|
else
|
|
hwif->dma_master = base;
|
|
return 0;
|
|
}
|
|
|
|
static int ide_iomio_dma(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
|
|
{
|
|
printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx",
|
|
hwif->name, base, base + ports - 1);
|
|
|
|
if (!request_region(base, ports, hwif->name)) {
|
|
printk(" -- Error, ports in use.\n");
|
|
return 1;
|
|
}
|
|
|
|
hwif->dma_base = base;
|
|
|
|
if (hwif->cds->extra) {
|
|
hwif->extra_base = base + (hwif->channel ? 8 : 16);
|
|
|
|
if (!hwif->mate || !hwif->mate->extra_ports) {
|
|
if (!request_region(hwif->extra_base,
|
|
hwif->cds->extra, hwif->cds->name)) {
|
|
printk(" -- Error, extra ports in use.\n");
|
|
release_region(base, ports);
|
|
return 1;
|
|
}
|
|
hwif->extra_ports = hwif->cds->extra;
|
|
}
|
|
}
|
|
|
|
if(hwif->mate)
|
|
hwif->dma_master = (hwif->channel) ? hwif->mate->dma_base:base;
|
|
else
|
|
hwif->dma_master = base;
|
|
return 0;
|
|
}
|
|
|
|
static int ide_dma_iobase(ide_hwif_t *hwif, unsigned long base, unsigned int ports)
|
|
{
|
|
if (hwif->mmio == 2)
|
|
return ide_mapped_mmio_dma(hwif, base,ports);
|
|
BUG_ON(hwif->mmio == 1);
|
|
return ide_iomio_dma(hwif, base, ports);
|
|
}
|
|
|
|
/*
|
|
* This can be called for a dynamically installed interface. Don't __init it
|
|
*/
|
|
void ide_setup_dma (ide_hwif_t *hwif, unsigned long dma_base, unsigned int num_ports)
|
|
{
|
|
if (ide_dma_iobase(hwif, dma_base, num_ports))
|
|
return;
|
|
|
|
if (ide_allocate_dma_engine(hwif)) {
|
|
ide_release_dma(hwif);
|
|
return;
|
|
}
|
|
|
|
if (!(hwif->dma_command))
|
|
hwif->dma_command = hwif->dma_base;
|
|
if (!(hwif->dma_vendor1))
|
|
hwif->dma_vendor1 = (hwif->dma_base + 1);
|
|
if (!(hwif->dma_status))
|
|
hwif->dma_status = (hwif->dma_base + 2);
|
|
if (!(hwif->dma_vendor3))
|
|
hwif->dma_vendor3 = (hwif->dma_base + 3);
|
|
if (!(hwif->dma_prdtable))
|
|
hwif->dma_prdtable = (hwif->dma_base + 4);
|
|
|
|
if (!hwif->ide_dma_off_quietly)
|
|
hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
|
|
if (!hwif->ide_dma_host_off)
|
|
hwif->ide_dma_host_off = &__ide_dma_host_off;
|
|
if (!hwif->ide_dma_on)
|
|
hwif->ide_dma_on = &__ide_dma_on;
|
|
if (!hwif->ide_dma_host_on)
|
|
hwif->ide_dma_host_on = &__ide_dma_host_on;
|
|
if (!hwif->ide_dma_check)
|
|
hwif->ide_dma_check = &__ide_dma_check;
|
|
if (!hwif->dma_setup)
|
|
hwif->dma_setup = &ide_dma_setup;
|
|
if (!hwif->dma_exec_cmd)
|
|
hwif->dma_exec_cmd = &ide_dma_exec_cmd;
|
|
if (!hwif->dma_start)
|
|
hwif->dma_start = &ide_dma_start;
|
|
if (!hwif->ide_dma_end)
|
|
hwif->ide_dma_end = &__ide_dma_end;
|
|
if (!hwif->ide_dma_test_irq)
|
|
hwif->ide_dma_test_irq = &__ide_dma_test_irq;
|
|
if (!hwif->ide_dma_timeout)
|
|
hwif->ide_dma_timeout = &__ide_dma_timeout;
|
|
if (!hwif->ide_dma_lostirq)
|
|
hwif->ide_dma_lostirq = &__ide_dma_lostirq;
|
|
|
|
if (hwif->chipset != ide_trm290) {
|
|
u8 dma_stat = hwif->INB(hwif->dma_status);
|
|
printk(", BIOS settings: %s:%s, %s:%s",
|
|
hwif->drives[0].name, (dma_stat & 0x20) ? "DMA" : "pio",
|
|
hwif->drives[1].name, (dma_stat & 0x40) ? "DMA" : "pio");
|
|
}
|
|
printk("\n");
|
|
|
|
BUG_ON(!hwif->dma_master);
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(ide_setup_dma);
|
|
#endif /* CONFIG_BLK_DEV_IDEDMA_PCI */
|