linux/arch
Russ Anderson 2022c1f136 [IA64] Update Altix nofault code
Montecito and Montvale behaves slightly differently than previous
Itanium processors, resulting in the MCA due to a failed PIO read
to sometimes surfacing outside the nofault code.  This code is
based on discussions with Intel CPU architects and verified at
customer sites.

Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2008-01-03 13:22:54 -08:00
..
alpha
arm
avr32
blackfin
cris
frv
h8300
ia64 [IA64] Update Altix nofault code 2008-01-03 13:22:54 -08:00
m32r
m68k
m68knommu
mips
parisc
powerpc [POWERPC] Fix build failure on Cell when CONFIG_SPU_FS=y 2008-01-02 15:56:30 +11:00
ppc
s390
sh
sh64
sparc
sparc64 [SPARC64]: Implement pci_resource_to_user() 2007-12-26 19:33:46 -08:00
um uml: user of helper_wait() got missed when it got extra arguments 2007-12-23 12:54:37 -08:00
v850
x86 fix lguest rmmod "bad pgd" 2008-01-01 11:30:35 -08:00
xtensa