f2f41c68ea
Move the base address defines of the ColdFire 54xx CPU slice timers into the 54xx specific header (m54xxsim.h). They are CPU specific, and belong with the CPU specific defines. Also make them relative to the MBAR peripheral region, making the define the absolute address. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/****************************************************************************/
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/*
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* mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
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*
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* (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
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*/
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/****************************************************************************/
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#ifndef mcfslt_h
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#define mcfslt_h
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/****************************************************************************/
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/*
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* Define the SLT timer register set addresses.
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*/
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#define MCFSLT_STCNT 0x00 /* Terminal count */
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#define MCFSLT_SCR 0x04 /* Control */
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#define MCFSLT_SCNT 0x08 /* Current count */
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#define MCFSLT_SSR 0x0C /* Status */
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/*
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* Bit definitions for the SCR control register.
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*/
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#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
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#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
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#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
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/*
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* Bit definitions for the SSR status register.
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*/
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#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
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#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
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/****************************************************************************/
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#endif /* mcfslt_h */
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