linux/drivers/clk/meson
Jerome Brunet 1f737ffa13 clk: meson: mpll: fix mpll0 fractional part ignored
mpll0 clock is special compared to the other mplls. It needs another
bit (ssen) to be set to activate the fractional part the mpll divider

Fixes: 007e6e5c5f ("clk: meson: mpll: add rw operation")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-08-01 14:18:31 +02:00
..
Kconfig * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) 2017-06-16 15:01:46 -07:00
Makefile clk: meson: add audio clock divider support 2017-04-07 16:50:44 +02:00
clk-audio-divider.c clk: meson: add audio clock divider support 2017-04-07 16:50:44 +02:00
clk-cpu.c clk: meson8b: clean up cpu clocks 2016-06-22 18:02:35 -07:00
clk-mpll.c clk: meson: mpll: fix mpll0 fractional part ignored 2017-08-01 14:18:31 +02:00
clk-pll.c clk: meson: Add support for parameters for specific PLLs 2017-04-04 12:05:12 -07:00
clkc.h clk: meson: mpll: fix mpll0 fractional part ignored 2017-08-01 14:18:31 +02:00
gxbb-aoclk.c clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe() 2016-08-24 00:55:13 -07:00
gxbb.c clk: meson: mpll: fix mpll0 fractional part ignored 2017-08-01 14:18:31 +02:00
gxbb.h clk: meson-gxbb: Add EE 32K Clock for CEC 2017-05-29 12:34:23 +00:00
meson8b.c clk: meson: mpll: fix mpll0 fractional part ignored 2017-08-01 14:18:31 +02:00
meson8b.h clk: meson8b: export the ethernet gate clock 2017-06-12 07:30:45 +00:00