d9116d07f6
This implements dynamic probing for the system FPGA. The system reset controller contains a fixed magic read word in order to identify the FPGA. This just utilizes a simple loop that scans across all of the fixed physical areas (area 0 through area 6) to locate the FPGA. The FPGA also contains register information detailing the area mappings and chip select settings for all of the other blocks, so this needs to be done before we can set up anything else. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
73 lines
1.7 KiB
C
73 lines
1.7 KiB
C
/*
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* SDK7786 FPGA Support.
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*
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* Copyright (C) 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/bcd.h>
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#include <mach/fpga.h>
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#include <asm/sizes.h>
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#define FPGA_REGS_OFFSET 0x03fff800
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#define FPGA_REGS_SIZE 0x490
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/*
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* The FPGA can be mapped in any of the generally available areas,
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* so we attempt to scan for it using the fixed SRSTR read magic.
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*
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* Once the FPGA is located, the rest of the mapping data for the other
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* components can be determined dynamically from its section mapping
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* registers.
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*/
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static void __iomem *sdk7786_fpga_probe(void)
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{
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unsigned long area;
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void __iomem *base;
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/*
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* Iterate over all of the areas where the FPGA could be mapped.
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* The possible range is anywhere from area 0 through 6, area 7
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* is reserved.
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*/
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for (area = PA_AREA0; area < PA_AREA7; area += SZ_64M) {
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base = ioremap_nocache(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE);
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if (!base) {
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/* Failed to remap this area, move along. */
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continue;
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}
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if (ioread16(base + SRSTR) == SRSTR_MAGIC)
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return base; /* Found it! */
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iounmap(base);
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}
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return NULL;
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}
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void __iomem *sdk7786_fpga_base;
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void __init sdk7786_fpga_init(void)
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{
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u16 version, date;
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sdk7786_fpga_base = sdk7786_fpga_probe();
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if (unlikely(!sdk7786_fpga_base)) {
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panic("FPGA detection failed.\n");
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return;
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}
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version = fpga_read_reg(FPGAVR);
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date = fpga_read_reg(FPGADR);
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pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n",
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bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf),
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((date >> 12) & 0xf) + 2000,
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(date >> 8) & 0xf, bcd2bin(date & 0xff));
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}
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