Weiyi Lu b3cf181c65 clk: mediatek: fix clk-gate flag setting ... CLK_SET_RATE_PARENT would be dropped. Merge two flag setting together to correct the error. Fixes: 5a1cc4c27a ("clk: mediatek: Add flags to mtk_gate") Cc: <stable@vger.kernel.org> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2019-04-12 09:41:49 -07:00
..
clk-apmixed.c
clk-cpumux.c
clk-cpumux.h
clk-gate.c	clk: mediatek: fix clk-gate flag setting	2019-04-12 09:41:49 -07:00
clk-gate.h	clk: mediatek: Add flags to mtk_gate	2019-02-26 09:53:39 -08:00
clk-mt2701-aud.c
clk-mt2701-bdp.c
clk-mt2701-eth.c
clk-mt2701-g3d.c
clk-mt2701-hif.c
clk-mt2701-img.c
clk-mt2701-mm.c
clk-mt2701-vdec.c
clk-mt2701.c	clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel	2019-02-25 09:19:33 -08:00
clk-mt2712-bdp.c
clk-mt2712-img.c
clk-mt2712-jpgdec.c
clk-mt2712-mfg.c
clk-mt2712-mm.c
clk-mt2712-vdec.c
clk-mt2712-venc.c
clk-mt2712.c	Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip' into clk-next	2019-03-08 10:34:22 -08:00
clk-mt6797-img.c
clk-mt6797-mm.c
clk-mt6797-vdec.c
clk-mt6797-venc.c
clk-mt6797.c	clk: mediatek: Mark bus and DRAM related clocks as critical	2019-02-26 09:54:50 -08:00
clk-mt7622-aud.c
clk-mt7622-eth.c
clk-mt7622-hif.c
clk-mt7622.c	clk: mediatek: Drop more __init markings for driver probe	2018-11-30 00:39:39 -08:00
clk-mt7629-eth.c
clk-mt7629-hif.c
clk-mt7629.c	clk: mediatek: fix the PCIe MAC clock parent	2018-12-05 12:30:30 -08:00
clk-mt8135.c
clk-mt8173.c	clk: mediatek: correct cpu clock name for MT8173 SoC	2019-02-26 10:17:40 -08:00
clk-mtk.c	Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next	2019-03-08 10:29:30 -08:00
clk-mtk.h	Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next	2019-03-08 10:29:30 -08:00
clk-pll.c
Kconfig
Makefile
reset.c