911e1c9b05
This patch exports SMBIOS provided firmware instance and label of onboard PCI devices to sysfs. New files are: /sys/bus/pci/devices/.../label which contains the firmware name for the device in question, and /sys/bus/pci/devices/.../index which contains the firmware device type instance for the given device. Signed-off-by: Jordan Hargrave <jordan_hargrave@dell.com> Signed-off-by: Narendra K <narendra_k@dell.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
350 lines
11 KiB
C
350 lines
11 KiB
C
#ifndef DRIVERS_PCI_H
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#define DRIVERS_PCI_H
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#include <linux/workqueue.h>
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#define PCI_CFG_SPACE_SIZE 256
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#define PCI_CFG_SPACE_EXP_SIZE 4096
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/* Functions internal to the PCI core code */
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extern int pci_uevent(struct device *dev, struct kobj_uevent_env *env);
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extern int pci_create_sysfs_dev_files(struct pci_dev *pdev);
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extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
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#ifndef CONFIG_DMI
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static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
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{ return 0; }
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static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
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{ return 0; }
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#else
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extern void pci_create_firmware_label_files(struct pci_dev *pdev);
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extern void pci_remove_firmware_label_files(struct pci_dev *pdev);
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#endif
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extern void pci_cleanup_rom(struct pci_dev *dev);
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#ifdef HAVE_PCI_MMAP
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extern int pci_mmap_fits(struct pci_dev *pdev, int resno,
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struct vm_area_struct *vma);
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#endif
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int pci_probe_reset_function(struct pci_dev *dev);
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/**
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* struct pci_platform_pm_ops - Firmware PM callbacks
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*
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* @is_manageable: returns 'true' if given device is power manageable by the
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* platform firmware
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*
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* @set_state: invokes the platform firmware to set the device's power state
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*
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* @choose_state: returns PCI power state of given device preferred by the
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* platform; to be used during system-wide transitions from a
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* sleeping state to the working state and vice versa
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*
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* @can_wakeup: returns 'true' if given device is capable of waking up the
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* system from a sleeping state
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*
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* @sleep_wake: enables/disables the system wake up capability of given device
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*
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* @run_wake: enables/disables the platform to generate run-time wake-up events
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* for given device (the device's wake-up capability has to be
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* enabled by @sleep_wake for this feature to work)
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*
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* If given platform is generally capable of power managing PCI devices, all of
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* these callbacks are mandatory.
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*/
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struct pci_platform_pm_ops {
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bool (*is_manageable)(struct pci_dev *dev);
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int (*set_state)(struct pci_dev *dev, pci_power_t state);
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pci_power_t (*choose_state)(struct pci_dev *dev);
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bool (*can_wakeup)(struct pci_dev *dev);
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int (*sleep_wake)(struct pci_dev *dev, bool enable);
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int (*run_wake)(struct pci_dev *dev, bool enable);
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};
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extern int pci_set_platform_pm(struct pci_platform_pm_ops *ops);
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extern void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
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extern void pci_disable_enabled_device(struct pci_dev *dev);
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extern bool pci_check_pme_status(struct pci_dev *dev);
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extern int pci_finish_runtime_suspend(struct pci_dev *dev);
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extern int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
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extern void pci_pme_wakeup_bus(struct pci_bus *bus);
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extern void pci_pm_init(struct pci_dev *dev);
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extern void platform_pci_wakeup_init(struct pci_dev *dev);
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extern void pci_allocate_cap_save_buffers(struct pci_dev *dev);
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static inline bool pci_is_bridge(struct pci_dev *pci_dev)
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{
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return !!(pci_dev->subordinate);
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}
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extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
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extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
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extern int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
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extern int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
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extern int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
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extern int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
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struct pci_vpd_ops {
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ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
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ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
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void (*release)(struct pci_dev *dev);
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};
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struct pci_vpd {
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unsigned int len;
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const struct pci_vpd_ops *ops;
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struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
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};
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extern int pci_vpd_pci22_init(struct pci_dev *dev);
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static inline void pci_vpd_release(struct pci_dev *dev)
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{
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if (dev->vpd)
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dev->vpd->ops->release(dev);
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}
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/* PCI /proc functions */
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#ifdef CONFIG_PROC_FS
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extern int pci_proc_attach_device(struct pci_dev *dev);
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extern int pci_proc_detach_device(struct pci_dev *dev);
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extern int pci_proc_detach_bus(struct pci_bus *bus);
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#else
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static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
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static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
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#endif
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/* Functions for PCI Hotplug drivers to use */
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extern unsigned int pci_do_scan_bus(struct pci_bus *bus);
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#ifdef HAVE_PCI_LEGACY
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extern void pci_create_legacy_files(struct pci_bus *bus);
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extern void pci_remove_legacy_files(struct pci_bus *bus);
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#else
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static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
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static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
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#endif
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/* Lock for read/write access to pci device and bus lists */
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extern struct rw_semaphore pci_bus_sem;
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extern unsigned int pci_pm_d3_delay;
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#ifdef CONFIG_PCI_MSI
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void pci_no_msi(void);
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extern void pci_msi_init_pci_dev(struct pci_dev *dev);
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#else
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static inline void pci_no_msi(void) { }
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static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
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#endif
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#ifdef CONFIG_PCIEAER
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void pci_no_aer(void);
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#else
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static inline void pci_no_aer(void) { }
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#endif
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static inline int pci_no_d1d2(struct pci_dev *dev)
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{
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unsigned int parent_dstates = 0;
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if (dev->bus->self)
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parent_dstates = dev->bus->self->no_d1d2;
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return (dev->no_d1d2 || parent_dstates);
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}
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extern struct device_attribute pci_dev_attrs[];
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extern struct device_attribute dev_attr_cpuaffinity;
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extern struct device_attribute dev_attr_cpulistaffinity;
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#ifdef CONFIG_HOTPLUG
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extern struct bus_attribute pci_bus_attrs[];
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#else
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#define pci_bus_attrs NULL
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#endif
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/**
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* pci_match_one_device - Tell if a PCI device structure has a matching
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* PCI device id structure
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* @id: single PCI device id structure to match
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* @dev: the PCI device structure to match against
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*
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* Returns the matching pci_device_id structure or %NULL if there is no match.
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*/
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static inline const struct pci_device_id *
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pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
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{
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if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
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(id->device == PCI_ANY_ID || id->device == dev->device) &&
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(id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
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(id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
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!((id->class ^ dev->class) & id->class_mask))
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return id;
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return NULL;
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}
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struct pci_dev *pci_find_upstream_pcie_bridge(struct pci_dev *pdev);
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/* PCI slot sysfs helper code */
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#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
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extern struct kset *pci_slots_kset;
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struct pci_slot_attribute {
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struct attribute attr;
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ssize_t (*show)(struct pci_slot *, char *);
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ssize_t (*store)(struct pci_slot *, const char *, size_t);
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};
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#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
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enum pci_bar_type {
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pci_bar_unknown, /* Standard PCI BAR probe */
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pci_bar_io, /* An io port BAR */
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pci_bar_mem32, /* A 32-bit memory BAR */
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pci_bar_mem64, /* A 64-bit memory BAR */
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};
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extern int pci_setup_device(struct pci_dev *dev);
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extern int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
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struct resource *res, unsigned int reg);
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extern int pci_resource_bar(struct pci_dev *dev, int resno,
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enum pci_bar_type *type);
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extern int pci_bus_add_child(struct pci_bus *bus);
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extern void pci_enable_ari(struct pci_dev *dev);
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/**
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* pci_ari_enabled - query ARI forwarding status
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* @bus: the PCI bus
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*
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* Returns 1 if ARI forwarding is enabled, or 0 if not enabled;
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*/
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static inline int pci_ari_enabled(struct pci_bus *bus)
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{
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return bus->self && bus->self->ari_enabled;
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}
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#ifdef CONFIG_PCI_QUIRKS
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extern int pci_is_reassigndev(struct pci_dev *dev);
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resource_size_t pci_specified_resource_alignment(struct pci_dev *dev);
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extern void pci_disable_bridge_window(struct pci_dev *dev);
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#endif
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/* Single Root I/O Virtualization */
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struct pci_sriov {
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int pos; /* capability position */
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int nres; /* number of resources */
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u32 cap; /* SR-IOV Capabilities */
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u16 ctrl; /* SR-IOV Control */
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u16 total; /* total VFs associated with the PF */
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u16 initial; /* initial VFs associated with the PF */
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u16 nr_virtfn; /* number of VFs available */
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u16 offset; /* first VF Routing ID offset */
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u16 stride; /* following VF stride */
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u32 pgsz; /* page size for BAR alignment */
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u8 link; /* Function Dependency Link */
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struct pci_dev *dev; /* lowest numbered PF */
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struct pci_dev *self; /* this PF */
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struct mutex lock; /* lock for VF bus */
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struct work_struct mtask; /* VF Migration task */
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u8 __iomem *mstate; /* VF Migration State Array */
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};
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/* Address Translation Service */
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struct pci_ats {
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int pos; /* capability position */
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int stu; /* Smallest Translation Unit */
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int qdep; /* Invalidate Queue Depth */
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int ref_cnt; /* Physical Function reference count */
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unsigned int is_enabled:1; /* Enable bit is set */
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};
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#ifdef CONFIG_PCI_IOV
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extern int pci_iov_init(struct pci_dev *dev);
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extern void pci_iov_release(struct pci_dev *dev);
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extern int pci_iov_resource_bar(struct pci_dev *dev, int resno,
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enum pci_bar_type *type);
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extern int pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
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extern void pci_restore_iov_state(struct pci_dev *dev);
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extern int pci_iov_bus_range(struct pci_bus *bus);
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extern int pci_enable_ats(struct pci_dev *dev, int ps);
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extern void pci_disable_ats(struct pci_dev *dev);
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extern int pci_ats_queue_depth(struct pci_dev *dev);
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/**
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* pci_ats_enabled - query the ATS status
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* @dev: the PCI device
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*
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* Returns 1 if ATS capability is enabled, or 0 if not.
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*/
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static inline int pci_ats_enabled(struct pci_dev *dev)
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{
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return dev->ats && dev->ats->is_enabled;
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}
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#else
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static inline int pci_iov_init(struct pci_dev *dev)
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{
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return -ENODEV;
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}
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static inline void pci_iov_release(struct pci_dev *dev)
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{
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}
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static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno,
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enum pci_bar_type *type)
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{
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return 0;
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}
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static inline void pci_restore_iov_state(struct pci_dev *dev)
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{
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}
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static inline int pci_iov_bus_range(struct pci_bus *bus)
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{
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return 0;
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}
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static inline int pci_enable_ats(struct pci_dev *dev, int ps)
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{
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return -ENODEV;
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}
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static inline void pci_disable_ats(struct pci_dev *dev)
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{
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}
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static inline int pci_ats_queue_depth(struct pci_dev *dev)
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{
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return -ENODEV;
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}
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static inline int pci_ats_enabled(struct pci_dev *dev)
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{
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return 0;
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}
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#endif /* CONFIG_PCI_IOV */
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static inline int pci_resource_alignment(struct pci_dev *dev,
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struct resource *res)
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{
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#ifdef CONFIG_PCI_IOV
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int resno = res - dev->resource;
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if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
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return pci_sriov_resource_alignment(dev, resno);
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#endif
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return resource_alignment(res);
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}
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extern void pci_enable_acs(struct pci_dev *dev);
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struct pci_dev_reset_methods {
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u16 vendor;
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u16 device;
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int (*reset)(struct pci_dev *dev, int probe);
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};
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#ifdef CONFIG_PCI_QUIRKS
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extern int pci_dev_specific_reset(struct pci_dev *dev, int probe);
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#else
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static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
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{
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return -ENOTTY;
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}
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#endif
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#endif /* DRIVERS_PCI_H */
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