linux/arch/mips/lantiq
Felix Fietkau 6c356eda22 MIPS: Lantiq: Fix cascaded IRQ setup
With the IRQ stack changes integrated, the XRX200 devices started
emitting a constant stream of kernel messages like this:

[  565.415310] Spurious IRQ: CAUSE=0x1100c300

This is caused by IP0 getting handled by plat_irq_dispatch() rather than
its vectored interrupt handler, which is fixed by commit de856416e714
("MIPS: IRQ Stack: Fix erroneous jal to plat_irq_dispatch").

Fix plat_irq_dispatch() to handle non-vectored IPI interrupts correctly
by setting up IP2-6 as proper chained IRQ handlers and calling do_IRQ
for all MIPS CPU interrupts.

Signed-off-by: Felix Fietkau <nbd@nbd.name>
Acked-by: John Crispin <john@phrozen.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15077/
[james.hogan@imgtec.com: tweaked commit message]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
2017-02-13 18:58:53 +00:00
..
falcon MIPS: Lantiq: Fix mask of GPE frequency 2016-12-11 11:20:25 +01:00
xway MIPS: Lantiq: Lock DMA register accesses for SMP 2017-01-25 02:51:12 +01:00
Kconfig MIPS: Lantiq: Make it possible to build in no device tree 2016-05-13 14:01:44 +02:00
Makefile MIPS: Change my email address 2016-05-13 14:02:18 +02:00
Platform
clk.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
clk.h MIPS: Change my email address 2016-05-13 14:02:18 +02:00
early_printk.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
irq.c MIPS: Lantiq: Fix cascaded IRQ setup 2017-02-13 18:58:53 +00:00
prom.c MIPS: store the appended dtb address in a variable 2016-08-02 14:00:16 +02:00
prom.h MIPS: Change my email address 2016-05-13 14:02:18 +02:00