352 lines
8.2 KiB
C
352 lines
8.2 KiB
C
/*
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* SBE 2T3E3 synchronous serial card driver for Linux
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*
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* Copyright (C) 2009-2010 Krzysztof Halasa <khc@pm.waw.pl>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This code is based on a driver written by SBE Inc.
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*/
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#include <linux/delay.h>
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#include "2t3e3.h"
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#include "ctrl.h"
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#define bootrom_set_bit(sc, reg, bit) \
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bootrom_write((sc), (reg), \
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bootrom_read((sc), (reg)) | (bit))
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#define bootrom_clear_bit(sc, reg, bit) \
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bootrom_write((sc), (reg), \
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bootrom_read((sc), (reg)) & ~(bit))
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static inline void cpld_set_bit(struct channel *channel, unsigned reg, u32 bit)
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{
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unsigned long flags;
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spin_lock_irqsave(&channel->card->bootrom_lock, flags);
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bootrom_set_bit(channel, CPLD_MAP_REG(reg, channel), bit);
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spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
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}
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static inline void cpld_clear_bit(struct channel *channel, unsigned reg, u32 bit)
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{
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unsigned long flags;
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spin_lock_irqsave(&channel->card->bootrom_lock, flags);
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bootrom_clear_bit(channel, CPLD_MAP_REG(reg, channel), bit);
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spin_unlock_irqrestore(&channel->card->bootrom_lock, flags);
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}
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void cpld_init(struct channel *sc)
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{
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u32 val;
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/* PCRA */
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val = SBE_2T3E3_CPLD_VAL_CRC32 |
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cpld_val_map[SBE_2T3E3_CPLD_VAL_LOOP_TIMING_SOURCE][sc->h.slot];
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRA, val);
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/* PCRB */
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val = 0;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRB, val);
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/* PCRC */
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val = 0;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC, val);
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/* PBWF */
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val = 0;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWF, val);
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/* PBWL */
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val = 0;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWL, val);
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/* PLTR */
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val = SBE_2T3E3_CPLD_VAL_LCV_COUNTER;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PLTR, val);
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udelay(1000);
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/* PLCR */
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val = 0;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PLCR, val);
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udelay(1000);
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/* PPFR */
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val = 0x55;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PPFR, val);
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/* TODO: this doesn't work!!! */
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/* SERIAL_CHIP_SELECT */
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val = 0;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_SERIAL_CHIP_SELECT, val);
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/* PICSR */
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val = SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED |
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SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED |
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SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PICSR, val);
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cpld_start_intr(sc);
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udelay(1000);
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}
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void cpld_start_intr(struct channel *sc)
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{
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u32 val;
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/* PIER */
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val = SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_ETHERNET_ENABLE |
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SBE_2T3E3_CPLD_VAL_INTERRUPT_FROM_FRAMER_ENABLE;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PIER, val);
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}
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void cpld_stop_intr(struct channel *sc)
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{
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u32 val;
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/* PIER */
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val = 0;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PIER, val);
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}
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void cpld_set_frame_mode(struct channel *sc, u32 mode)
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{
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if (sc->p.frame_mode == mode)
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return;
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switch (mode) {
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case SBE_2T3E3_FRAME_MODE_HDLC:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_TRANSPARENT_MODE |
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SBE_2T3E3_CPLD_VAL_RAW_MODE);
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exar7250_unipolar_onoff(sc, SBE_2T3E3_OFF);
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exar7300_unipolar_onoff(sc, SBE_2T3E3_OFF);
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break;
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case SBE_2T3E3_FRAME_MODE_TRANSPARENT:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_RAW_MODE);
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_TRANSPARENT_MODE);
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exar7250_unipolar_onoff(sc, SBE_2T3E3_OFF);
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exar7300_unipolar_onoff(sc, SBE_2T3E3_OFF);
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break;
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case SBE_2T3E3_FRAME_MODE_RAW:
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_RAW_MODE);
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exar7250_unipolar_onoff(sc, SBE_2T3E3_ON);
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exar7300_unipolar_onoff(sc, SBE_2T3E3_ON);
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break;
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default:
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return;
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}
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sc->p.frame_mode = mode;
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}
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/* set rate of the local clock */
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void cpld_set_frame_type(struct channel *sc, u32 type)
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{
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switch (type) {
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case SBE_2T3E3_FRAME_TYPE_E3_G751:
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case SBE_2T3E3_FRAME_TYPE_E3_G832:
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_LOCAL_CLOCK_E3);
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break;
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case SBE_2T3E3_FRAME_TYPE_T3_CBIT:
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case SBE_2T3E3_FRAME_TYPE_T3_M13:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_LOCAL_CLOCK_E3);
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break;
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default:
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return;
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}
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}
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void cpld_set_scrambler(struct channel *sc, u32 mode)
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{
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if (sc->p.scrambler == mode)
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return;
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switch (mode) {
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case SBE_2T3E3_SCRAMBLER_OFF:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
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SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE);
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break;
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case SBE_2T3E3_SCRAMBLER_LARSCOM:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
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SBE_2T3E3_CPLD_VAL_SCRAMBLER_TYPE);
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
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SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE);
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break;
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case SBE_2T3E3_SCRAMBLER_ADC_KENTROX_DIGITAL:
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
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SBE_2T3E3_CPLD_VAL_SCRAMBLER_TYPE);
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
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SBE_2T3E3_CPLD_VAL_SCRAMBLER_ENABLE);
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break;
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default:
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return;
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}
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sc->p.scrambler = mode;
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}
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void cpld_set_crc(struct channel *sc, u32 crc)
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{
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if (sc->p.crc == crc)
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return;
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switch (crc) {
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case SBE_2T3E3_CRC_16:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_CRC32);
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break;
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case SBE_2T3E3_CRC_32:
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_CRC32);
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break;
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default:
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return;
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}
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sc->p.crc = crc;
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}
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void cpld_select_panel(struct channel *sc, u32 panel)
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{
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if (sc->p.panel == panel)
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return;
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switch (panel) {
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case SBE_2T3E3_PANEL_FRONT:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_REAR_PANEL);
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break;
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case SBE_2T3E3_PANEL_REAR:
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_REAR_PANEL);
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break;
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default:
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return;
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}
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udelay(100);
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sc->p.panel = panel;
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}
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void cpld_set_clock(struct channel *sc, u32 mode)
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{
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if (sc->p.clock_source == mode)
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return;
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switch (mode) {
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case SBE_2T3E3_TIMING_LOCAL:
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_ALT);
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break;
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case SBE_2T3E3_TIMING_LOOP:
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRA,
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SBE_2T3E3_CPLD_VAL_ALT);
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break;
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default:
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return;
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}
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sc->p.clock_source = mode;
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}
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void cpld_set_pad_count(struct channel *sc, u32 count)
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{
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u32 val;
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if (sc->p.pad_count == count)
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return;
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switch (count) {
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case SBE_2T3E3_PAD_COUNT_1:
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val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_1;
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break;
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case SBE_2T3E3_PAD_COUNT_2:
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val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_2;
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break;
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case SBE_2T3E3_PAD_COUNT_3:
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val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_3;
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break;
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case SBE_2T3E3_PAD_COUNT_4:
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val = SBE_2T3E3_CPLD_VAL_PAD_COUNT_4;
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break;
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default:
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return;
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}
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cpld_clear_bit(sc, SBE_2T3E3_CPLD_REG_PCRB,
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SBE_2T3E3_CPLD_VAL_PAD_COUNT);
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cpld_set_bit(sc, SBE_2T3E3_CPLD_REG_PCRB, val);
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sc->p.pad_count = count;
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}
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void cpld_LOS_update(struct channel *sc)
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{
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u_int8_t los;
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PICSR,
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SBE_2T3E3_CPLD_VAL_DMO_SIGNAL_DETECTED |
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SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_LOCK_DETECTED |
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SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED);
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los = cpld_read(sc, SBE_2T3E3_CPLD_REG_PICSR) &
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SBE_2T3E3_CPLD_VAL_RECEIVE_LOSS_OF_SIGNAL_DETECTED;
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if (los != sc->s.LOS)
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dev_info(&sc->pdev->dev, "SBE 2T3E3: LOS status: %s\n",
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los ? "Loss of signal" : "Signal OK");
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sc->s.LOS = los;
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}
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void cpld_set_fractional_mode(struct channel *sc, u32 mode,
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u32 start, u32 stop)
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{
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if (mode == SBE_2T3E3_FRACTIONAL_MODE_NONE) {
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start = 0;
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stop = 0;
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}
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if (sc->p.fractional_mode == mode && sc->p.bandwidth_start == start &&
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sc->p.bandwidth_stop == stop)
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return;
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switch (mode) {
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case SBE_2T3E3_FRACTIONAL_MODE_NONE:
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
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SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_NONE);
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break;
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case SBE_2T3E3_FRACTIONAL_MODE_0:
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
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SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_0);
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break;
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case SBE_2T3E3_FRACTIONAL_MODE_1:
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
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SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_1);
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break;
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case SBE_2T3E3_FRACTIONAL_MODE_2:
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PCRC,
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SBE_2T3E3_CPLD_VAL_FRACTIONAL_MODE_2);
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break;
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default:
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netdev_err(sc->dev, "wrong mode in set_fractional_mode\n");
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return;
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}
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWF, start);
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cpld_write(sc, SBE_2T3E3_CPLD_REG_PBWL, stop);
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sc->p.fractional_mode = mode;
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sc->p.bandwidth_start = start;
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sc->p.bandwidth_stop = stop;
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}
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