Giulio Benetti 1169602150 drm/sun4i: tcon: fix inverted DCLK polarity ... [ Upstream commit 67f4aeb2b41a0629abde3794d463547f60b0cbdd ] During commit 88bc417856 ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_* macros have been changed to avoid ambiguity but just because of this ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning _SAMPLE_ not _DRIVE_. This leads to DLCK inversion and need to fix but instead of swapping phase values, let's adopt an easier approach Maxime suggested: It turned out that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to invert DCLK polarity and this makes things really easier than before. So let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE as bit 26 and activating according to bus_flags the same way it is done for all the other signals polarity. Fixes: 88bc417856 ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") Suggested-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://patchwork.freedesktop.org/patch/msgid/20210114081732.9386-1-giulio.benetti@benettiengineering.com Signed-off-by: Sasha Levin <sashal@kernel.org>		2021-03-04 10:26:21 +01:00
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Kconfig	…
Makefile	…
sun4i_backend.c	drm/sun4i: backend: Disable alpha on the lowest plane on the A20	2020-09-17 13:47:43 +02:00
sun4i_backend.h	…
sun4i_crtc.c	…
sun4i_crtc.h	…
sun4i_dotclock.c	…
sun4i_dotclock.h	…
sun4i_drv.c	…
sun4i_drv.h	…
sun4i_framebuffer.c	…
sun4i_framebuffer.h	…
sun4i_frontend.c	drm/sun4i: frontend: Fix the scaler phase on A33	2020-11-10 12:37:29 +01:00
sun4i_frontend.h	drm/sun4i: frontend: Rework a bit the phase data	2020-11-10 12:37:29 +01:00
sun4i_hdmi.h	…
sun4i_hdmi_ddc_clk.c	…
sun4i_hdmi_enc.c	…
sun4i_hdmi_i2c.c	…
sun4i_hdmi_tmds_clk.c	…
sun4i_layer.c	…
sun4i_layer.h	…
sun4i_lvds.c	…
sun4i_lvds.h	…
sun4i_rgb.c	…
sun4i_rgb.h	…
sun4i_tcon.c	drm/sun4i: tcon: fix inverted DCLK polarity	2021-03-04 10:26:21 +01:00
sun4i_tcon.h	drm/sun4i: tcon: fix inverted DCLK polarity	2021-03-04 10:26:21 +01:00
sun4i_tv.c	…
sun6i_drc.c	…
sun6i_mipi_dsi.c	…
sun6i_mipi_dsi.h	…
sun8i_csc.c	…
sun8i_csc.h	drm/sun4i: sun8i-csc: Secondary CSC register correction	2020-10-01 13:18:18 +02:00
sun8i_dw_hdmi.c	drm/sun4i: dw-hdmi: Fix max. frequency for H6	2021-02-17 10:35:18 +01:00
sun8i_dw_hdmi.h	…
sun8i_hdmi_phy.c	drm/sun4i: Fix H6 HDMI PHY configuration	2021-02-17 10:35:18 +01:00
sun8i_hdmi_phy_clk.c	…
sun8i_mixer.c	drm/sun4i: mixer: Extend regmap max_register	2020-10-07 08:01:26 +02:00
sun8i_mixer.h	…
sun8i_tcon_top.c	…
sun8i_tcon_top.h	…
sun8i_ui_layer.c	…
sun8i_ui_layer.h	…
sun8i_ui_scaler.c	…
sun8i_ui_scaler.h	…
sun8i_vi_layer.c	…
sun8i_vi_layer.h	…
sun8i_vi_scaler.c	…
sun8i_vi_scaler.h	…
sunxi_engine.h	…