30e748a507
This matters to any sort of device that is wired to one of the CPU interrupt pins on an SMP system. Typically the scenario is most easily triggered with the count/compare timer interrupt where the same interrupt number and thus irq_desc is used on each processor. CPU A CPU B do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) set IRQ_INPROGRESS spin_unlock(desc_lock) do_IRQ() generic_handle_irq() handle_level_irq() spin_lock(desc_lock) IRQ_INPROGRESS set => bail out spin_lock(desc_lock) clear IRQ_INPROGRESS spin_unlock(desc_lock) In case of the cp0 compare interrupt this means the interrupt will be acked and not handled or re-armed on CPU b, so there won't be any timer interrupt until the count register wraps around. With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just working right on VSMP because the count registers are synchronized on bootup so it takes something that disables interrupts for a long time on one processor to trigger this one. For scenarios where an interrupt is multicasted or broadcasted over several CPUs the existing code was safe and the fix will break it. There is no way to know in the interrupt controller code because it is abstracted from the platform code. I think we do not have such a setup currently, so this should be ok. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
/*
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* Copyright (C) 2003 Ralf Baechle
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Handler for RM9000 extended interrupts. These are a non-standard
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* feature so we handle them separately from standard interrupts.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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static inline void unmask_rm9k_irq(unsigned int irq)
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{
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set_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
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}
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static inline void mask_rm9k_irq(unsigned int irq)
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{
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clear_c0_intcontrol(0x1000 << (irq - RM9K_CPU_IRQ_BASE));
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}
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static inline void rm9k_cpu_irq_enable(unsigned int irq)
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{
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unsigned long flags;
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local_irq_save(flags);
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unmask_rm9k_irq(irq);
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local_irq_restore(flags);
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}
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/*
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* Performance counter interrupts are global on all processors.
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*/
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static void local_rm9k_perfcounter_irq_startup(void *args)
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{
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unsigned int irq = (unsigned int) args;
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rm9k_cpu_irq_enable(irq);
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}
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static unsigned int rm9k_perfcounter_irq_startup(unsigned int irq)
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{
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on_each_cpu(local_rm9k_perfcounter_irq_startup, (void *) irq, 0, 1);
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return 0;
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}
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static void local_rm9k_perfcounter_irq_shutdown(void *args)
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{
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unsigned int irq = (unsigned int) args;
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unsigned long flags;
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local_irq_save(flags);
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mask_rm9k_irq(irq);
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local_irq_restore(flags);
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}
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static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
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{
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on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
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}
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static struct irq_chip rm9k_irq_controller = {
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.name = "RM9000",
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.ack = mask_rm9k_irq,
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.mask = mask_rm9k_irq,
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.mask_ack = mask_rm9k_irq,
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.unmask = unmask_rm9k_irq,
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};
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static struct irq_chip rm9k_perfcounter_irq = {
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.name = "RM9000",
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.startup = rm9k_perfcounter_irq_startup,
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.shutdown = rm9k_perfcounter_irq_shutdown,
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.ack = mask_rm9k_irq,
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.mask = mask_rm9k_irq,
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.mask_ack = mask_rm9k_irq,
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.unmask = unmask_rm9k_irq,
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};
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unsigned int rm9000_perfcount_irq;
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EXPORT_SYMBOL(rm9000_perfcount_irq);
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void __init rm9k_cpu_irq_init(void)
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{
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int base = RM9K_CPU_IRQ_BASE;
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int i;
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clear_c0_intcontrol(0x0000f000); /* Mask all */
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for (i = base; i < base + 4; i++)
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set_irq_chip_and_handler(i, &rm9k_irq_controller,
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handle_level_irq);
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rm9000_perfcount_irq = base + 1;
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set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
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handle_percpu_irq);
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}
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