linux/arch/riscv
Yash Shah 00a5bf3a8c RISC-V: Add PCIe I/O BAR memory mapping
For legacy I/O BARs (non-MMIO BARs) to work correctly on RISC-V Linux,
we need to establish a reserved memory region for them, so that drivers
that wish to use the legacy I/O BARs can issue reads and writes against
a memory region that is mapped to the host PCIe controller's I/O BAR
mapping.

Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-28 10:43:32 -07:00
..
boot riscv: dts: HiFive Unleashed: add default chosen/stdout-path 2019-10-14 12:30:30 -07:00
configs RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig 2019-09-19 05:44:35 -07:00
include RISC-V: Add PCIe I/O BAR memory mapping 2019-10-28 10:43:32 -07:00
kernel riscv: for C functions called only from assembly, mark with __visible 2019-10-28 00:46:02 -07:00
lib riscv: Using CSR numbers to access CSRs 2019-08-30 11:04:19 -07:00
mm riscv: add missing header file includes 2019-10-28 00:46:01 -07:00
net bpf, riscv: Enable zext optimization for more RV64G ALU ops 2019-07-05 23:55:41 +02:00
Kbuild riscv: add arch/riscv/Kbuild 2019-08-30 17:34:00 -07:00
Kconfig riscv: make mmap allocation top-down by default 2019-09-24 15:54:12 -07:00
Kconfig.debug RISC-V: Remove EARLY_PRINTK support 2018-12-17 10:23:46 -08:00
Kconfig.socs riscv: select SiFive platform drivers with SOC_SIFIVE 2019-07-01 13:20:01 -07:00
Makefile Kbuild updates for v5.4 2019-09-20 08:36:47 -07:00