6f7c8623db
The PB1200 is basically a DB1200 with additional MMC and camera sockets and different base addresses for external hardware (CPLD, IDE, Net, NAND). This patch implements the missing PB1200 features in DB1200 support code and runtime board detection. Tested on DB1200 only. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2880/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/*
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* AMD Alchemy DBAu1200 Reference Board
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* Board register defines.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#ifndef __ASM_DB1200_H
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#define __ASM_DB1200_H
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#include <linux/types.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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/* Bit positions for the different interrupt sources */
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#define BCSR_INT_IDE 0x0001
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#define BCSR_INT_ETH 0x0002
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#define BCSR_INT_PC0 0x0004
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#define BCSR_INT_PC0STSCHG 0x0008
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#define BCSR_INT_PC1 0x0010
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#define BCSR_INT_PC1STSCHG 0x0020
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#define BCSR_INT_DC 0x0040
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#define BCSR_INT_FLASHBUSY 0x0080
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#define BCSR_INT_PC0INSERT 0x0100
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#define BCSR_INT_PC0EJECT 0x0200
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#define BCSR_INT_PC1INSERT 0x0400
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#define BCSR_INT_PC1EJECT 0x0800
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#define BCSR_INT_SD0INSERT 0x1000
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#define BCSR_INT_SD0EJECT 0x2000
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#define BCSR_INT_SD1INSERT 0x4000
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#define BCSR_INT_SD1EJECT 0x8000
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#define IDE_REG_SHIFT 5
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#define DB1200_IDE_PHYS_ADDR 0x18800000
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#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
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#define DB1200_ETH_PHYS_ADDR 0x19000300
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#define DB1200_NAND_PHYS_ADDR 0x20000000
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#define PB1200_IDE_PHYS_ADDR 0x0C800000
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#define PB1200_ETH_PHYS_ADDR 0x0D000300
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#define PB1200_NAND_PHYS_ADDR 0x1C000000
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/*
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* External Interrupts for DBAu1200 as of 8/6/2004.
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* Bit positions in the CPLD registers can be calculated by taking
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* the interrupt define and subtracting the DB1200_INT_BEGIN value.
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*
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* Example: IDE bis pos is = 64 - 64
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* ETH bit pos is = 65 - 64
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*/
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enum external_db1200_ints {
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DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
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DB1200_IDE_INT = DB1200_INT_BEGIN,
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DB1200_ETH_INT,
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DB1200_PC0_INT,
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DB1200_PC0_STSCHG_INT,
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DB1200_PC1_INT,
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DB1200_PC1_STSCHG_INT,
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DB1200_DC_INT,
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DB1200_FLASHBUSY_INT,
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DB1200_PC0_INSERT_INT,
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DB1200_PC0_EJECT_INT,
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DB1200_PC1_INSERT_INT,
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DB1200_PC1_EJECT_INT,
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DB1200_SD0_INSERT_INT,
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DB1200_SD0_EJECT_INT,
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PB1200_SD1_INSERT_INT,
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PB1200_SD1_EJECT_INT,
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DB1200_INT_END = DB1200_INT_BEGIN + 15,
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};
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#endif /* __ASM_DB1200_H */
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