945a51517c
after review of all intel drivers, found several instances where drivers had the incorrect pattern of: memory mapped write(); delay(); which should always be: memory mapped write(); write flush(); /* aka memory mapped read */ delay(); explanation: The reason for including the flush is that writes can be held (posted) in PCI/PCIe bridges, but the read always has to complete synchronously and therefore has to flush all pending writes to a device. If a write is held and followed by a delay, the delay means nothing because the write may not have reached hardware (maybe even not until the next read) Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
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| .. | ||
| e1000_82575.c | ||
| e1000_82575.h | ||
| e1000_defines.h | ||
| e1000_hw.h | ||
| e1000_mac.c | ||
| e1000_mac.h | ||
| e1000_mbx.c | ||
| e1000_mbx.h | ||
| e1000_nvm.c | ||
| e1000_nvm.h | ||
| e1000_phy.c | ||
| e1000_phy.h | ||
| e1000_regs.h | ||
| igb_ethtool.c | ||
| igb_main.c | ||
| igb.h | ||
| Makefile | ||