linux/drivers/clk/tegra
Peter Geis 8ab3478335 clk: tegra30: Add hda clock default rates to clock driver
[ Upstream commit f4eccc7fea203cfb35205891eced1ab51836f362 ]

Current implementation defaults the hda clocks to clk_m. This causes hda
to run too slow to operate correctly. Fix this by defaulting to pll_p and
setting the frequency to the correct rate.

This matches upstream t124 and downstream t30.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Ion Agorria <ion@agorria.com>
Acked-by: Sameer Pujar <spujar@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210108135913.2421585-2-pgwipeout@gmail.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-01-27 11:47:44 +01:00
..
Kconfig
Makefile
clk-audio-sync.c
clk-bpmp.c
clk-dfll.c clk: tegra: Do not return 0 on failure 2020-12-30 11:51:46 +01:00
clk-dfll.h
clk-divider.c
clk-emc.c
clk-id.h clk: tegra: Fix duplicated SE clock entry 2020-12-30 11:51:24 +01:00
clk-periph-fixed.c
clk-periph-gate.c
clk-periph.c
clk-pll-out.c
clk-pll.c clk: tegra: Always program PLL_E when enabled 2020-10-07 08:01:28 +02:00
clk-sdmmc-mux.c
clk-super.c
clk-tegra-audio.c
clk-tegra-fixed.c
clk-tegra-periph.c clk: tegra: Fix duplicated SE clock entry 2020-12-30 11:51:24 +01:00
clk-tegra-pmc.c
clk-tegra-super-gen4.c
clk-tegra20.c
clk-tegra30.c clk: tegra30: Add hda clock default rates to clock driver 2021-01-27 11:47:44 +01:00
clk-tegra114.c
clk-tegra124-dfll-fcpu.c
clk-tegra124.c
clk-tegra210.c
clk-utils.c
clk.c
clk.h
cvb.c
cvb.h