2d3cbc7804
Signed-off-by: Richard Kuo <rkuo@codeaurora.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/*
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* Cache flush operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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* 02110-1301, USA.
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*/
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#ifndef _ASM_CACHEFLUSH_H
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#define _ASM_CACHEFLUSH_H
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#include <linux/cache.h>
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#include <linux/mm.h>
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#include <asm/string.h>
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#include <asm-generic/cacheflush.h>
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/* Cache flushing:
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*
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* - flush_cache_all() flushes entire cache
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* - flush_cache_mm(mm) flushes the specified mm context's cache lines
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* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
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* - flush_cache_range(vma, start, end) flushes a range of pages
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* - flush_icache_range(start, end) flush a range of instructions
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* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
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* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
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*
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* Need to doublecheck which one is really needed for ptrace stuff to work.
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*/
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#define LINESIZE 32
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#define LINEBITS 5
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/*
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* Flush Dcache range through current map.
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*/
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extern void flush_dcache_range(unsigned long start, unsigned long end);
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/*
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* Flush Icache range through current map.
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*/
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#undef flush_icache_range
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extern void flush_icache_range(unsigned long start, unsigned long end);
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/*
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* Memory-management related flushes are there to ensure in non-physically
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* indexed cache schemes that stale lines belonging to a given ASID aren't
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* in the cache to confuse things. The prototype Hexagon Virtual Machine
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* only uses a single ASID for all user-mode maps, which should
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* mean that they aren't necessary. A brute-force, flush-everything
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* implementation, with the name xxxxx_hexagon() is present in
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* arch/hexagon/mm/cache.c, but let's not wire it up until we know
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* it is needed.
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*/
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extern void flush_cache_all_hexagon(void);
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/*
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* This may or may not ever have to be non-null, depending on the
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* virtual machine MMU. For a native kernel, it's definitiely a no-op
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*
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* This is also the place where deferred cache coherency stuff seems
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* to happen, classically... but instead we do it like ia64 and
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* clean the cache when the PTE is set.
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*
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*/
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t *ptep)
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{
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/* generic_ptrace_pokedata doesn't wind up here, does it? */
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}
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#undef copy_to_user_page
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static inline void copy_to_user_page(struct vm_area_struct *vma,
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struct page *page,
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unsigned long vaddr,
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void *dst, void *src, int len)
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{
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memcpy(dst, src, len);
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if (vma->vm_flags & VM_EXEC) {
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flush_icache_range((unsigned long) dst,
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(unsigned long) dst + len);
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}
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}
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extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
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extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);
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#endif
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